forked from Minki/linux
5c73cc4b6c
As always, this tends to be one of our bigger branches. There are lots of
updates this release, but not that many jumps out as something that needs
more detailed coverage. Some of the highlights are:
- DTs for the new Annapurna Labs Alpine platform
- More graphics DT pieces falling into place on Exynos, bridges, clocks.
- Plenty of DT updates for Qualcomm platforms for various IP blocks
- Some churn on Tegra due to switch-over to tool-generated pinctrl data
- Misc fixes and updates for Atmel at91 platforms
- Various DT updates to add IP block support on Broadcom's Cygnus platforms
- More updates for Renesas platforms as DT support is added for various IP
blocks (IPMMU, display, audio, etc).
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Olof Johansson:
"As always, this tends to be one of our bigger branches. There are
lots of updates this release, but not that many jumps out as something
that needs more detailed coverage. Some of the highlights are:
- DTs for the new Annapurna Labs Alpine platform
- more graphics DT pieces falling into place on Exynos, bridges,
clocks.
- plenty of DT updates for Qualcomm platforms for various IP blocks
- some churn on Tegra due to switch-over to tool-generated pinctrl
data
- misc fixes and updates for Atmel at91 platforms
- various DT updates to add IP block support on Broadcom's Cygnus
platforms
- more updates for Renesas platforms as DT support is added for
various IP blocks (IPMMU, display, audio, etc)"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (231 commits)
ARM: dts: alpine: add internal pci
Revert "ARM: dts: mt8135: Add pinctrl/GPIO/EINT node for mt8135."
ARM: mvebu: use 0xf1000000 as internal registers on Armada 370 DB
ARM: dts: qcom: Add idle state device nodes for 8064
ARM: dts: qcom: Add idle states device nodes for 8084
ARM: dts: qcom: Add idle states device nodes for 8974/8074
ARM: dts: qcom: Update power-controller device node for 8064 Krait CPUs
ARM: dts: qcom: Add power-controller device node for 8084 Krait CPUs
ARM: dts: qcom: Add power-controller device node for 8074 Krait CPUs
devicetree: bindings: Document qcom,idle-states
devicetree: bindings: Update qcom,saw2 node bindings
dt-bindings: Add #defines for MSM8916 clocks and resets
arm: dts: qcom: Add LPASS Audio HW to IPQ8064 device tree
arm: dts: qcom: Add APQ8084 chipset SPMI PMIC's nodes
arm: dts: qcom: Add 8x74 chipset SPMI PMIC's nodes
arm: dts: qcom: Add SPMI PMIC Arbiter nodes for APQ8084 and MSM8974
arm: dts: qcom: Add LCC nodes
arm: dts: qcom: Add TCSR support for MSM8960
arm: dts: qcom: Add TCSR support for MSM8660
arm: dts: qcom: Add TCSR support for IPQ8064
...
972 lines
24 KiB
Plaintext
972 lines
24 KiB
Plaintext
/*
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* at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
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*
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* Copyright (C) 2012 Atmel,
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* 2012 Hong Xu <hong.xu@atmel.com>
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*
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* Licensed under GPLv2 or later.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/at91.h>
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/ {
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model = "Atmel AT91SAM9N12 SoC";
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compatible = "atmel,at91sam9n12";
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interrupt-parent = <&aic>;
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aliases {
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serial0 = &dbgu;
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serial1 = &usart0;
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serial2 = &usart1;
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serial3 = &usart2;
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serial4 = &usart3;
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gpio0 = &pioA;
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gpio1 = &pioB;
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gpio2 = &pioC;
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gpio3 = &pioD;
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tcb0 = &tcb0;
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tcb1 = &tcb1;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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ssc0 = &ssc0;
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pwm0 = &pwm0;
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};
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cpus {
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#address-cells = <0>;
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#size-cells = <0>;
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cpu {
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compatible = "arm,arm926ej-s";
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device_type = "cpu";
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};
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};
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memory {
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reg = <0x20000000 0x10000000>;
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};
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clocks {
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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};
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sram: sram@00300000 {
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compatible = "mmio-sram";
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reg = <0x00300000 0x8000>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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aic: interrupt-controller@fffff000 {
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#interrupt-cells = <3>;
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compatible = "atmel,at91rm9200-aic";
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interrupt-controller;
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reg = <0xfffff000 0x200>;
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atmel,external-irqs = <31>;
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};
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ramc0: ramc@ffffe800 {
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compatible = "atmel,at91sam9g45-ddramc";
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reg = <0xffffe800 0x200>;
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clocks = <&ddrck>;
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clock-names = "ddrck";
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};
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pmc: pmc@fffffc00 {
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compatible = "atmel,at91sam9n12-pmc";
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reg = <0xfffffc00 0x200>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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interrupt-controller;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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main_rc_osc: main_rc_osc {
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compatible = "atmel,at91sam9x5-clk-main-rc-osc";
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#clock-cells = <0>;
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interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
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clock-frequency = <12000000>;
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clock-accuracy = <50000000>;
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};
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main_osc: main_osc {
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compatible = "atmel,at91rm9200-clk-main-osc";
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#clock-cells = <0>;
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interrupts-extended = <&pmc AT91_PMC_MOSCS>;
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clocks = <&main_xtal>;
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};
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main: mainck {
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compatible = "atmel,at91sam9x5-clk-main";
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#clock-cells = <0>;
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interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
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clocks = <&main_rc_osc>, <&main_osc>;
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};
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plla: pllack {
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compatible = "atmel,at91rm9200-clk-pll";
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#clock-cells = <0>;
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interrupts-extended = <&pmc AT91_PMC_LOCKA>;
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clocks = <&main>;
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reg = <0>;
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atmel,clk-input-range = <2000000 32000000>;
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#atmel,pll-clk-output-range-cells = <4>;
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atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
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<695000000 750000000 1 0>,
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<645000000 700000000 2 0>,
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<595000000 650000000 3 0>,
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<545000000 600000000 0 1>,
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<495000000 555000000 1 1>,
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<445000000 500000000 2 1>,
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<400000000 450000000 3 1>;
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};
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plladiv: plladivck {
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compatible = "atmel,at91sam9x5-clk-plldiv";
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#clock-cells = <0>;
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clocks = <&plla>;
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};
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pllb: pllbck {
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compatible = "atmel,at91rm9200-clk-pll";
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#clock-cells = <0>;
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interrupts-extended = <&pmc AT91_PMC_LOCKB>;
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clocks = <&main>;
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reg = <1>;
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atmel,clk-input-range = <2000000 32000000>;
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#atmel,pll-clk-output-range-cells = <3>;
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atmel,pll-clk-output-ranges = <30000000 100000000 0>;
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};
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mck: masterck {
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compatible = "atmel,at91sam9x5-clk-master";
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#clock-cells = <0>;
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interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
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clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>;
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atmel,clk-output-range = <0 133333333>;
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atmel,clk-divisors = <1 2 4 3>;
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atmel,master-clk-have-div3-pres;
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};
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usb: usbck {
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compatible = "atmel,at91sam9n12-clk-usb";
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#clock-cells = <0>;
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clocks = <&pllb>;
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};
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prog: progck {
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compatible = "atmel,at91sam9x5-clk-programmable";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&pmc>;
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clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>;
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prog0: prog0 {
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#clock-cells = <0>;
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reg = <0>;
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interrupts = <AT91_PMC_PCKRDY(0)>;
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};
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prog1: prog1 {
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#clock-cells = <0>;
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reg = <1>;
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interrupts = <AT91_PMC_PCKRDY(1)>;
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};
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};
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systemck {
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compatible = "atmel,at91rm9200-clk-system";
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#address-cells = <1>;
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#size-cells = <0>;
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ddrck: ddrck {
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#clock-cells = <0>;
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reg = <2>;
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clocks = <&mck>;
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};
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lcdck: lcdck {
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#clock-cells = <0>;
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reg = <3>;
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clocks = <&mck>;
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};
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uhpck: uhpck {
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#clock-cells = <0>;
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reg = <6>;
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clocks = <&usb>;
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};
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udpck: udpck {
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#clock-cells = <0>;
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reg = <7>;
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clocks = <&usb>;
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};
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pck0: pck0 {
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#clock-cells = <0>;
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reg = <8>;
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clocks = <&prog0>;
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};
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pck1: pck1 {
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#clock-cells = <0>;
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reg = <9>;
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clocks = <&prog1>;
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};
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};
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periphck {
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compatible = "atmel,at91sam9x5-clk-peripheral";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&mck>;
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pioAB_clk: pioAB_clk {
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#clock-cells = <0>;
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reg = <2>;
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};
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pioCD_clk: pioCD_clk {
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#clock-cells = <0>;
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reg = <3>;
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};
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fuse_clk: fuse_clk {
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#clock-cells = <0>;
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reg = <4>;
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};
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usart0_clk: usart0_clk {
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#clock-cells = <0>;
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reg = <5>;
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};
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usart1_clk: usart1_clk {
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#clock-cells = <0>;
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reg = <6>;
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};
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usart2_clk: usart2_clk {
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#clock-cells = <0>;
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reg = <7>;
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};
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usart3_clk: usart3_clk {
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#clock-cells = <0>;
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reg = <8>;
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};
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twi0_clk: twi0_clk {
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reg = <9>;
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#clock-cells = <0>;
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};
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twi1_clk: twi1_clk {
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#clock-cells = <0>;
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reg = <10>;
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};
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mci0_clk: mci0_clk {
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#clock-cells = <0>;
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reg = <12>;
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};
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spi0_clk: spi0_clk {
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#clock-cells = <0>;
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reg = <13>;
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};
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spi1_clk: spi1_clk {
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#clock-cells = <0>;
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reg = <14>;
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};
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uart0_clk: uart0_clk {
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#clock-cells = <0>;
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reg = <15>;
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};
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uart1_clk: uart1_clk {
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#clock-cells = <0>;
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reg = <16>;
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};
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tcb_clk: tcb_clk {
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#clock-cells = <0>;
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reg = <17>;
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};
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pwm_clk: pwm_clk {
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#clock-cells = <0>;
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reg = <18>;
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};
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adc_clk: adc_clk {
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#clock-cells = <0>;
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reg = <19>;
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};
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dma0_clk: dma0_clk {
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#clock-cells = <0>;
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reg = <20>;
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};
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uhphs_clk: uhphs_clk {
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#clock-cells = <0>;
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reg = <22>;
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};
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udphs_clk: udphs_clk {
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#clock-cells = <0>;
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reg = <23>;
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};
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lcdc_clk: lcdc_clk {
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#clock-cells = <0>;
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reg = <25>;
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};
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sha_clk: sha_clk {
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#clock-cells = <0>;
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reg = <27>;
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};
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ssc0_clk: ssc0_clk {
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#clock-cells = <0>;
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reg = <28>;
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};
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aes_clk: aes_clk {
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#clock-cells = <0>;
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reg = <29>;
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};
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trng_clk: trng_clk {
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#clock-cells = <0>;
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reg = <30>;
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};
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};
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};
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rstc@fffffe00 {
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compatible = "atmel,at91sam9g45-rstc";
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reg = <0xfffffe00 0x10>;
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};
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pit: timer@fffffe30 {
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compatible = "atmel,at91sam9260-pit";
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reg = <0xfffffe30 0xf>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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clocks = <&mck>;
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};
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shdwc@fffffe10 {
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compatible = "atmel,at91sam9x5-shdwc";
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reg = <0xfffffe10 0x10>;
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};
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sckc@fffffe50 {
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compatible = "atmel,at91sam9x5-sckc";
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reg = <0xfffffe50 0x4>;
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slow_osc: slow_osc {
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compatible = "atmel,at91sam9x5-clk-slow-osc";
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#clock-cells = <0>;
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clocks = <&slow_xtal>;
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};
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slow_rc_osc: slow_rc_osc {
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compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-accuracy = <50000000>;
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};
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clk32k: slck {
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compatible = "atmel,at91sam9x5-clk-slow";
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#clock-cells = <0>;
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clocks = <&slow_rc_osc>, <&slow_osc>;
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};
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};
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mmc0: mmc@f0008000 {
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compatible = "atmel,hsmci";
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reg = <0xf0008000 0x600>;
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interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
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dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
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dma-names = "rxtx";
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clocks = <&mci0_clk>;
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clock-names = "mci_clk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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tcb0: timer@f8008000 {
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compatible = "atmel,at91sam9x5-tcb";
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reg = <0xf8008000 0x100>;
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&tcb_clk>;
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clock-names = "t0_clk";
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};
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tcb1: timer@f800c000 {
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compatible = "atmel,at91sam9x5-tcb";
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reg = <0xf800c000 0x100>;
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&tcb_clk>;
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clock-names = "t0_clk";
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};
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dma: dma-controller@ffffec00 {
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compatible = "atmel,at91sam9g45-dma";
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reg = <0xffffec00 0x200>;
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interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
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#dma-cells = <2>;
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clocks = <&dma0_clk>;
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clock-names = "dma_clk";
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};
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pinctrl@fffff400 {
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|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
|
|
ranges = <0xfffff400 0xfffff400 0x800>;
|
|
|
|
atmel,mux-mask = <
|
|
/* A B C */
|
|
0xffffffff 0xffe07983 0x00000000 /* pioA */
|
|
0x00040000 0x00047e0f 0x00000000 /* pioB */
|
|
0xfdffffff 0x07c00000 0xb83fffff /* pioC */
|
|
0x003fffff 0x003f8000 0x00000000 /* pioD */
|
|
>;
|
|
|
|
/* shared pinctrl settings */
|
|
dbgu {
|
|
pinctrl_dbgu: dbgu-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
|
|
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */
|
|
};
|
|
};
|
|
|
|
usart0 {
|
|
pinctrl_usart0: usart0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
|
|
AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */
|
|
};
|
|
|
|
pinctrl_usart0_rts: usart0_rts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
|
|
};
|
|
|
|
pinctrl_usart0_cts: usart0_cts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
|
|
};
|
|
};
|
|
|
|
usart1 {
|
|
pinctrl_usart1: usart1-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
|
|
AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
|
|
};
|
|
};
|
|
|
|
usart2 {
|
|
pinctrl_usart2: usart2-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
|
|
AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */
|
|
};
|
|
|
|
pinctrl_usart2_rts: usart2_rts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
|
|
};
|
|
|
|
pinctrl_usart2_cts: usart2_cts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
|
|
};
|
|
};
|
|
|
|
usart3 {
|
|
pinctrl_usart3: usart3-0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */
|
|
AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */
|
|
};
|
|
|
|
pinctrl_usart3_rts: usart3_rts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
|
|
};
|
|
|
|
pinctrl_usart3_cts: usart3_cts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
pinctrl_uart0: uart0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */
|
|
AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
pinctrl_uart1: uart1-0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */
|
|
AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */
|
|
};
|
|
};
|
|
|
|
nand {
|
|
pinctrl_nand: nand-0 {
|
|
atmel,pins =
|
|
<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/
|
|
AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */
|
|
};
|
|
};
|
|
|
|
mmc0 {
|
|
pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
|
|
AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
|
|
AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
|
|
};
|
|
|
|
pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
|
|
AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
|
|
AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
|
|
};
|
|
|
|
pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
|
|
AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
|
|
AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */
|
|
AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */
|
|
};
|
|
};
|
|
|
|
ssc0 {
|
|
pinctrl_ssc0_tx: ssc0_tx-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
|
|
AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
|
|
AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
|
|
};
|
|
|
|
pinctrl_ssc0_rx: ssc0_rx-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
|
|
AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
|
|
AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
|
|
};
|
|
};
|
|
|
|
spi0 {
|
|
pinctrl_spi0: spi0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
|
|
AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
|
|
AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
|
|
};
|
|
};
|
|
|
|
spi1 {
|
|
pinctrl_spi1: spi1-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
|
|
AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
|
|
AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
|
|
};
|
|
};
|
|
|
|
i2c0 {
|
|
pinctrl_i2c0: i2c0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
|
|
AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
pinctrl_i2c1: i2c1-0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE
|
|
AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
};
|
|
|
|
tcb0 {
|
|
pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
|
|
atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
|
|
atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
|
|
atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
|
|
atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
|
|
atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
|
|
atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
|
|
atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
|
|
atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
|
|
atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
|
|
};
|
|
};
|
|
|
|
tcb1 {
|
|
pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
|
|
atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
|
|
atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
|
|
atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
|
|
atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
|
|
atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
|
|
atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
|
|
atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
|
|
atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
|
|
pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
|
|
atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
|
|
};
|
|
};
|
|
|
|
pioA: gpio@fffff400 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfffff400 0x200>;
|
|
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioAB_clk>;
|
|
};
|
|
|
|
pioB: gpio@fffff600 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfffff600 0x200>;
|
|
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioAB_clk>;
|
|
};
|
|
|
|
pioC: gpio@fffff800 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfffff800 0x200>;
|
|
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioCD_clk>;
|
|
};
|
|
|
|
pioD: gpio@fffffa00 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfffffa00 0x200>;
|
|
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioCD_clk>;
|
|
};
|
|
};
|
|
|
|
dbgu: serial@fffff200 {
|
|
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
|
|
reg = <0xfffff200 0x200>;
|
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_dbgu>;
|
|
clocks = <&mck>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
ssc0: ssc@f0010000 {
|
|
compatible = "atmel,at91sam9g45-ssc";
|
|
reg = <0xf0010000 0x4000>;
|
|
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
dmas = <&dma 0 AT91_DMA_CFG_PER_ID(21)>,
|
|
<&dma 0 AT91_DMA_CFG_PER_ID(22)>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
|
|
clocks = <&ssc0_clk>;
|
|
clock-names = "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
usart0: serial@f801c000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf801c000 0x4000>;
|
|
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usart0>;
|
|
clocks = <&usart0_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
usart1: serial@f8020000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8020000 0x4000>;
|
|
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usart1>;
|
|
clocks = <&usart1_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
usart2: serial@f8024000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8024000 0x4000>;
|
|
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usart2>;
|
|
clocks = <&usart2_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
usart3: serial@f8028000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8028000 0x4000>;
|
|
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usart3>;
|
|
clocks = <&usart3_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@f8010000 {
|
|
compatible = "atmel,at91sam9x5-i2c";
|
|
reg = <0xf8010000 0x100>;
|
|
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
|
|
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>,
|
|
<&dma 1 AT91_DMA_CFG_PER_ID(14)>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c0>;
|
|
clocks = <&twi0_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@f8014000 {
|
|
compatible = "atmel,at91sam9x5-i2c";
|
|
reg = <0xf8014000 0x100>;
|
|
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
|
|
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>,
|
|
<&dma 1 AT91_DMA_CFG_PER_ID(16)>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c1>;
|
|
clocks = <&twi1_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@f0000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xf0000000 0x100>;
|
|
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
|
|
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>,
|
|
<&dma 1 AT91_DMA_CFG_PER_ID(2)>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi0>;
|
|
clocks = <&spi0_clk>;
|
|
clock-names = "spi_clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@f0004000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xf0004000 0x100>;
|
|
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
|
|
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>,
|
|
<&dma 1 AT91_DMA_CFG_PER_ID(4)>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi1>;
|
|
clocks = <&spi1_clk>;
|
|
clock-names = "spi_clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
watchdog@fffffe40 {
|
|
compatible = "atmel,at91sam9260-wdt";
|
|
reg = <0xfffffe40 0x10>;
|
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
atmel,watchdog-type = "hardware";
|
|
atmel,reset-type = "all";
|
|
atmel,dbg-halt;
|
|
status = "disabled";
|
|
};
|
|
|
|
rtc@fffffeb0 {
|
|
compatible = "atmel,at91rm9200-rtc";
|
|
reg = <0xfffffeb0 0x40>;
|
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@f8034000 {
|
|
compatible = "atmel,at91sam9rl-pwm";
|
|
reg = <0xf8034000 0x300>;
|
|
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&pwm_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb1: gadget@f803c000 {
|
|
compatible = "atmel,at91sam9260-udc";
|
|
reg = <0xf803c000 0x4000>;
|
|
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
|
|
clocks = <&udphs_clk>, <&udpck>;
|
|
clock-names = "pclk", "hclk";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
nand0: nand@40000000 {
|
|
compatible = "atmel,at91rm9200-nand";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = < 0x40000000 0x10000000
|
|
0xffffe000 0x00000600
|
|
0xffffe600 0x00000200
|
|
0x00108000 0x00018000
|
|
>;
|
|
atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
|
|
atmel,nand-addr-offset = <21>;
|
|
atmel,nand-cmd-offset = <22>;
|
|
atmel,nand-has-dma;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_nand>;
|
|
gpios = <&pioD 5 GPIO_ACTIVE_HIGH
|
|
&pioD 4 GPIO_ACTIVE_HIGH
|
|
0
|
|
>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb0: ohci@00500000 {
|
|
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
|
|
reg = <0x00500000 0x00100000>;
|
|
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
|
|
clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
|
|
<&uhpck>;
|
|
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
i2c@0 {
|
|
compatible = "i2c-gpio";
|
|
gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
|
|
&pioA 31 GPIO_ACTIVE_HIGH /* scl */
|
|
>;
|
|
i2c-gpio,sda-open-drain;
|
|
i2c-gpio,scl-open-drain;
|
|
i2c-gpio,delay-us = <2>; /* ~100 kHz */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|