forked from Minki/linux
01799b6222
New platform uses RBCPR hardware feature, with that voting for absolute voltage of VDD CX is not required. Hence vote for corner of VDD CX which uses nominal corner voltage on VDD CX. Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Cc: Mayank Rana <mrana@codeaurora.org> Signed-off-by: Felipe Balbi <balbi@ti.com>
96 lines
3.3 KiB
Plaintext
96 lines
3.3 KiB
Plaintext
MSM SoC HSUSB controllers
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EHCI
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Required properties:
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- compatible: Should contain "qcom,ehci-host"
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- regs: offset and length of the register set in the memory map
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- usb-phy: phandle for the PHY device
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Example EHCI controller device node:
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ehci: ehci@f9a55000 {
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compatible = "qcom,ehci-host";
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reg = <0xf9a55000 0x400>;
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usb-phy = <&usb_otg>;
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};
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USB PHY with optional OTG:
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Required properties:
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- compatible: Should contain:
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"qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
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"qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
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- regs: Offset and length of the register set in the memory map
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- interrupts: interrupt-specifier for the OTG interrupt.
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- clocks: A list of phandle + clock-specifier pairs for the
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clocks listed in clock-names
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- clock-names: Should contain the following:
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"phy" USB PHY reference clock
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"core" Protocol engine clock
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"iface" Interface bus clock
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"alt_core" Protocol engine clock for targets with asynchronous
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reset methodology. (optional)
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- vdccx-supply: phandle to the regulator for the vdd supply for
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digital circuit operation.
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- v1p8-supply: phandle to the regulator for the 1.8V supply
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- v3p3-supply: phandle to the regulator for the 3.3V supply
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- resets: A list of phandle + reset-specifier pairs for the
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resets listed in reset-names
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- reset-names: Should contain the following:
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"phy" USB PHY controller reset
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"link" USB LINK controller reset
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- qcom,otg-control: OTG control (VBUS and ID notifications) can be one of
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1 - PHY control
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2 - PMIC control
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Optional properties:
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- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
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- qcom,phy-init-sequence: PHY configuration sequence values. This is related to Device
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Mode Eye Diagram test. Start address at which these values will be
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written is ULPI_EXT_VENDOR_SPECIFIC. Value of -1 is reserved as
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"do not overwrite default value at this address".
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For example: qcom,phy-init-sequence = < -1 0x63 >;
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Will update only value at address ULPI_EXT_VENDOR_SPECIFIC + 1.
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- qcom,phy-num: Select number of pyco-phy to use, can be one of
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0 - PHY one, default
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1 - Second PHY
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Some platforms may have configuration to allow USB
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controller work with any of the two HSPHYs present.
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- qcom,vdd-levels: This property must be a list of three integer values
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(no, min, max) where each value represents either a voltage
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in microvolts or a value corresponding to voltage corner.
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Example HSUSB OTG controller device node:
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usb@f9a55000 {
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compatible = "qcom,usb-otg-snps";
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reg = <0xf9a55000 0x400>;
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interrupts = <0 134 0>;
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dr_mode = "peripheral";
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clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,
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<&gcc GCC_USB_HS_AHB_CLK>;
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clock-names = "phy", "core", "iface";
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vddcx-supply = <&pm8841_s2_corner>;
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v1p8-supply = <&pm8941_l6>;
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v3p3-supply = <&pm8941_l24>;
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resets = <&gcc GCC_USB2A_PHY_BCR>, <&gcc GCC_USB_HS_BCR>;
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reset-names = "phy", "link";
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qcom,otg-control = <1>;
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qcom,phy-init-sequence = < -1 0x63 >;
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qcom,vdd-levels = <1 5 7>;
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};
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