This corrects the pinmux for accessing the TPM over the I2C line. Thus, it allows correctly probing the module, that previously failed with I2C errors. Signed-off-by: Jerome Coste <jerome.coste@etu.utc.fr> Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Signed-off-by: Thierry Reding <treding@nvidia.com>
		
			
				
	
	
		
			1341 lines
		
	
	
		
			40 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
			
		
		
	
	
			1341 lines
		
	
	
		
			40 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| /dts-v1/;
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| 
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| #include "tegra124-nyan.dtsi"
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| 
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| #include "tegra124-nyan-blaze-emc.dtsi"
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| 
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| / {
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| 	model = "HP Chromebook 14";
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| 	compatible = "google,nyan-blaze-rev10", "google,nyan-blaze-rev9",
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| 		     "google,nyan-blaze-rev8", "google,nyan-blaze-rev7",
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| 		     "google,nyan-blaze-rev6", "google,nyan-blaze-rev5",
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| 		     "google,nyan-blaze-rev4", "google,nyan-blaze-rev3",
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| 		     "google,nyan-blaze-rev2", "google,nyan-blaze-rev1",
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| 		     "google,nyan-blaze-rev0", "google,nyan-blaze",
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| 		     "google,nyan", "nvidia,tegra124";
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| 
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| 	panel: panel {
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| 		compatible = "samsung,ltn140at29-301";
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| 
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| 		backlight = <&backlight>;
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| 		ddc-i2c-bus = <&dpaux>;
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| 	};
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| 
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| 	sound {
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| 		compatible = "nvidia,tegra-audio-max98090-nyan-blaze",
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| 			     "nvidia,tegra-audio-max98090-nyan",
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| 			     "nvidia,tegra-audio-max98090";
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| 		nvidia,model = "GoogleNyanBlaze";
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| 	};
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| 
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| 	pinmux@70000868 {
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| 		pinctrl-names = "default";
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| 		pinctrl-0 = <&pinmux_default>;
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| 
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| 		pinmux_default: common {
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| 			clk_32k_out_pa0 {
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| 				nvidia,pins = "clk_32k_out_pa0";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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| 			};
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| 			uart3_cts_n_pa1 {
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| 				nvidia,pins = "uart3_cts_n_pa1";
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| 				nvidia,function = "gmi";
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| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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| 			};
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| 			dap2_fs_pa2 {
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| 				nvidia,pins = "dap2_fs_pa2";
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| 				nvidia,function = "i2s1";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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| 			};
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| 			dap2_sclk_pa3 {
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| 				nvidia,pins = "dap2_sclk_pa3";
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| 				nvidia,function = "i2s1";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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| 			};
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| 			dap2_din_pa4 {
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| 				nvidia,pins = "dap2_din_pa4";
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| 				nvidia,function = "i2s1";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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| 			};
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| 			dap2_dout_pa5 {
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| 				nvidia,pins = "dap2_dout_pa5";
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| 				nvidia,function = "i2s1";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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| 			};
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| 			sdmmc3_clk_pa6 {
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| 				nvidia,pins = "sdmmc3_clk_pa6";
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| 				nvidia,function = "sdmmc3";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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| 			};
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| 			sdmmc3_cmd_pa7 {
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| 				nvidia,pins = "sdmmc3_cmd_pa7";
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| 				nvidia,function = "sdmmc3";
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| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			pb0 {
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| 				nvidia,pins = "pb0";
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| 				nvidia,function = "rsvd2";
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| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
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| 			pb1 {
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| 				nvidia,pins = "pb1";
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| 				nvidia,function = "rsvd2";
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| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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| 			};
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| 			sdmmc3_dat3_pb4 {
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| 				nvidia,pins = "sdmmc3_dat3_pb4";
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| 				nvidia,function = "sdmmc3";
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| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc3_dat2_pb5 {
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| 				nvidia,pins = "sdmmc3_dat2_pb5";
 | |
| 				nvidia,function = "sdmmc3";
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| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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| 			};
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| 			sdmmc3_dat1_pb6 {
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| 				nvidia,pins = "sdmmc3_dat1_pb6";
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| 				nvidia,function = "sdmmc3";
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| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
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| 			sdmmc3_dat0_pb7 {
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| 				nvidia,pins = "sdmmc3_dat0_pb7";
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| 				nvidia,function = "sdmmc3";
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| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
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| 			uart3_rts_n_pc0 {
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| 				nvidia,pins = "uart3_rts_n_pc0";
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| 				nvidia,function = "gmi";
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| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
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| 			uart2_txd_pc2 {
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| 				nvidia,pins = "uart2_txd_pc2";
 | |
| 				nvidia,function = "irda";
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| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
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| 			uart2_rxd_pc3 {
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| 				nvidia,pins = "uart2_rxd_pc3";
 | |
| 				nvidia,function = "irda";
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| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			gen1_i2c_scl_pc4 {
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| 				nvidia,pins = "gen1_i2c_scl_pc4";
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| 				nvidia,function = "i2c1";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			gen1_i2c_sda_pc5 {
 | |
| 				nvidia,pins = "gen1_i2c_sda_pc5";
 | |
| 				nvidia,function = "i2c1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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| 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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| 			};
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| 			pc7 {
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| 				nvidia,pins = "pc7";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
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| 			pg0 {
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| 				nvidia,pins = "pg0";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
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| 			pg1 {
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| 				nvidia,pins = "pg1";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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| 			};
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| 			pg2 {
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| 				nvidia,pins = "pg2";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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| 			};
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| 			pg3 {
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| 				nvidia,pins = "pg3";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
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| 			pg4 {
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| 				nvidia,pins = "pg4";
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| 				nvidia,function = "spi4";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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| 			};
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| 			pg5 {
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| 				nvidia,pins = "pg5";
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| 				nvidia,function = "spi4";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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| 			};
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| 			pg6 {
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| 				nvidia,pins = "pg6";
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| 				nvidia,function = "spi4";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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| 			};
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| 			pg7 {
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| 				nvidia,pins = "pg7";
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| 				nvidia,function = "spi4";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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| 			};
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| 			ph0 {
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| 				nvidia,pins = "ph0";
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| 				nvidia,function = "gmi";
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| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
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| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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| 			};
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| 			ph1 {
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| 				nvidia,pins = "ph1";
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| 				nvidia,function = "pwm1";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			ph2 {
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| 				nvidia,pins = "ph2";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
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| 			ph3 {
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| 				nvidia,pins = "ph3";
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| 				nvidia,function = "gmi";
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| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			ph4 {
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| 				nvidia,pins = "ph4";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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| 			};
 | |
| 			ph5 {
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| 				nvidia,pins = "ph5";
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| 				nvidia,function = "rsvd2";
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| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			ph6 {
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| 				nvidia,pins = "ph6";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			ph7 {
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| 				nvidia,pins = "ph7";
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| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pi0 {
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| 				nvidia,pins = "pi0";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			pi1 {
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| 				nvidia,pins = "pi1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			pi2 {
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| 				nvidia,pins = "pi2";
 | |
| 				nvidia,function = "rsvd4";
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| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pi3 {
 | |
| 				nvidia,pins = "pi3";
 | |
| 				nvidia,function = "spi4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pi4 {
 | |
| 				nvidia,pins = "pi4";
 | |
| 				nvidia,function = "gmi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pi5 {
 | |
| 				nvidia,pins = "pi5";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pi6 {
 | |
| 				nvidia,pins = "pi6";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			pi7 {
 | |
| 				nvidia,pins = "pi7";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			pj0 {
 | |
| 				nvidia,pins = "pj0";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			pj2 {
 | |
| 				nvidia,pins = "pj2";
 | |
| 				nvidia,function = "rsvd1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			uart2_cts_n_pj5 {
 | |
| 				nvidia,pins = "uart2_cts_n_pj5";
 | |
| 				nvidia,function = "gmi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			uart2_rts_n_pj6 {
 | |
| 				nvidia,pins = "uart2_rts_n_pj6";
 | |
| 				nvidia,function = "gmi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pj7 {
 | |
| 				nvidia,pins = "pj7";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			pk0 {
 | |
| 				nvidia,pins = "pk0";
 | |
| 				nvidia,function = "rsvd1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pk1 {
 | |
| 				nvidia,pins = "pk1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pk2 {
 | |
| 				nvidia,pins = "pk2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			pk3 {
 | |
| 				nvidia,pins = "pk3";
 | |
| 				nvidia,function = "gmi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pk4 {
 | |
| 				nvidia,pins = "pk4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			spdif_out_pk5 {
 | |
| 				nvidia,pins = "spdif_out_pk5";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			spdif_in_pk6 {
 | |
| 				nvidia,pins = "spdif_in_pk6";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pk7 {
 | |
| 				nvidia,pins = "pk7";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			dap1_fs_pn0 {
 | |
| 				nvidia,pins = "dap1_fs_pn0";
 | |
| 				nvidia,function = "rsvd4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			dap1_din_pn1 {
 | |
| 				nvidia,pins = "dap1_din_pn1";
 | |
| 				nvidia,function = "rsvd4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			dap1_dout_pn2 {
 | |
| 				nvidia,pins = "dap1_dout_pn2";
 | |
| 				nvidia,function = "i2s0";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			dap1_sclk_pn3 {
 | |
| 				nvidia,pins = "dap1_sclk_pn3";
 | |
| 				nvidia,function = "rsvd4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			usb_vbus_en0_pn4 {
 | |
| 				nvidia,pins = "usb_vbus_en0_pn4";
 | |
| 				nvidia,function = "usb";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			usb_vbus_en1_pn5 {
 | |
| 				nvidia,pins = "usb_vbus_en1_pn5";
 | |
| 				nvidia,function = "usb";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			hdmi_int_pn7 {
 | |
| 				nvidia,pins = "hdmi_int_pn7";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			ulpi_data7_po0 {
 | |
| 				nvidia,pins = "ulpi_data7_po0";
 | |
| 				nvidia,function = "ulpi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			ulpi_data0_po1 {
 | |
| 				nvidia,pins = "ulpi_data0_po1";
 | |
| 				nvidia,function = "ulpi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			ulpi_data1_po2 {
 | |
| 				nvidia,pins = "ulpi_data1_po2";
 | |
| 				nvidia,function = "ulpi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			ulpi_data2_po3 {
 | |
| 				nvidia,pins = "ulpi_data2_po3";
 | |
| 				nvidia,function = "ulpi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			ulpi_data3_po4 {
 | |
| 				nvidia,pins = "ulpi_data3_po4";
 | |
| 				nvidia,function = "ulpi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			ulpi_data4_po5 {
 | |
| 				nvidia,pins = "ulpi_data4_po5";
 | |
| 				nvidia,function = "ulpi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			ulpi_data5_po6 {
 | |
| 				nvidia,pins = "ulpi_data5_po6";
 | |
| 				nvidia,function = "ulpi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			ulpi_data6_po7 {
 | |
| 				nvidia,pins = "ulpi_data6_po7";
 | |
| 				nvidia,function = "ulpi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			dap3_fs_pp0 {
 | |
| 				nvidia,pins = "dap3_fs_pp0";
 | |
| 				nvidia,function = "i2s2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			dap3_din_pp1 {
 | |
| 				nvidia,pins = "dap3_din_pp1";
 | |
| 				nvidia,function = "i2s2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			dap3_dout_pp2 {
 | |
| 				nvidia,pins = "dap3_dout_pp2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			dap3_sclk_pp3 {
 | |
| 				nvidia,pins = "dap3_sclk_pp3";
 | |
| 				nvidia,function = "rsvd3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			dap4_fs_pp4 {
 | |
| 				nvidia,pins = "dap4_fs_pp4";
 | |
| 				nvidia,function = "rsvd4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			dap4_din_pp5 {
 | |
| 				nvidia,pins = "dap4_din_pp5";
 | |
| 				nvidia,function = "rsvd3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			dap4_dout_pp6 {
 | |
| 				nvidia,pins = "dap4_dout_pp6";
 | |
| 				nvidia,function = "rsvd4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			dap4_sclk_pp7 {
 | |
| 				nvidia,pins = "dap4_sclk_pp7";
 | |
| 				nvidia,function = "rsvd3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_col0_pq0 {
 | |
| 				nvidia,pins = "kb_col0_pq0";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			kb_col1_pq1 {
 | |
| 				nvidia,pins = "kb_col1_pq1";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_col2_pq2 {
 | |
| 				nvidia,pins = "kb_col2_pq2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			kb_col3_pq3 {
 | |
| 				nvidia,pins = "kb_col3_pq3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			kb_col4_pq4 {
 | |
| 				nvidia,pins = "kb_col4_pq4";
 | |
| 				nvidia,function = "sdmmc3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			kb_col5_pq5 {
 | |
| 				nvidia,pins = "kb_col5_pq5";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_col6_pq6 {
 | |
| 				nvidia,pins = "kb_col6_pq6";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			kb_col7_pq7 {
 | |
| 				nvidia,pins = "kb_col7_pq7";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			kb_row0_pr0 {
 | |
| 				nvidia,pins = "kb_row0_pr0";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_row1_pr1 {
 | |
| 				nvidia,pins = "kb_row1_pr1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			kb_row2_pr2 {
 | |
| 				nvidia,pins = "kb_row2_pr2";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_row3_pr3 {
 | |
| 				nvidia,pins = "kb_row3_pr3";
 | |
| 				nvidia,function = "kbc";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_row4_pr4 {
 | |
| 				nvidia,pins = "kb_row4_pr4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			kb_row5_pr5 {
 | |
| 				nvidia,pins = "kb_row5_pr5";
 | |
| 				nvidia,function = "rsvd3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_row6_pr6 {
 | |
| 				nvidia,pins = "kb_row6_pr6";
 | |
| 				nvidia,function = "kbc";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_row7_pr7 {
 | |
| 				nvidia,pins = "kb_row7_pr7";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			kb_row8_ps0 {
 | |
| 				nvidia,pins = "kb_row8_ps0";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_row9_ps1 {
 | |
| 				nvidia,pins = "kb_row9_ps1";
 | |
| 				nvidia,function = "uarta";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_row10_ps2 {
 | |
| 				nvidia,pins = "kb_row10_ps2";
 | |
| 				nvidia,function = "uarta";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			kb_row11_ps3 {
 | |
| 				nvidia,pins = "kb_row11_ps3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_row12_ps4 {
 | |
| 				nvidia,pins = "kb_row12_ps4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_row13_ps5 {
 | |
| 				nvidia,pins = "kb_row13_ps5";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_row14_ps6 {
 | |
| 				nvidia,pins = "kb_row14_ps6";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_row15_ps7 {
 | |
| 				nvidia,pins = "kb_row15_ps7";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			kb_row16_pt0 {
 | |
| 				nvidia,pins = "kb_row16_pt0";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			kb_row17_pt1 {
 | |
| 				nvidia,pins = "kb_row17_pt1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			gen2_i2c_scl_pt5 {
 | |
| 				nvidia,pins = "gen2_i2c_scl_pt5";
 | |
| 				nvidia,function = "i2c2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			gen2_i2c_sda_pt6 {
 | |
| 				nvidia,pins = "gen2_i2c_sda_pt6";
 | |
| 				nvidia,function = "i2c2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc4_cmd_pt7 {
 | |
| 				nvidia,pins = "sdmmc4_cmd_pt7";
 | |
| 				nvidia,function = "sdmmc4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			pu0 {
 | |
| 				nvidia,pins = "pu0";
 | |
| 				nvidia,function = "rsvd4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pu1 {
 | |
| 				nvidia,pins = "pu1";
 | |
| 				nvidia,function = "rsvd1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pu2 {
 | |
| 				nvidia,pins = "pu2";
 | |
| 				nvidia,function = "rsvd1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pu3 {
 | |
| 				nvidia,pins = "pu3";
 | |
| 				nvidia,function = "gmi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pu4 {
 | |
| 				nvidia,pins = "pu4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			pu5 {
 | |
| 				nvidia,pins = "pu5";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			pu6 {
 | |
| 				nvidia,pins = "pu6";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			pv0 {
 | |
| 				nvidia,pins = "pv0";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			pv1 {
 | |
| 				nvidia,pins = "pv1";
 | |
| 				nvidia,function = "rsvd1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			sdmmc3_cd_n_pv2 {
 | |
| 				nvidia,pins = "sdmmc3_cd_n_pv2";
 | |
| 				nvidia,function = "sdmmc3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc1_wp_n_pv3 {
 | |
| 				nvidia,pins = "sdmmc1_wp_n_pv3";
 | |
| 				nvidia,function = "sdmmc1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			ddc_scl_pv4 {
 | |
| 				nvidia,pins = "ddc_scl_pv4";
 | |
| 				nvidia,function = "i2c4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			ddc_sda_pv5 {
 | |
| 				nvidia,pins = "ddc_sda_pv5";
 | |
| 				nvidia,function = "i2c4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			gpio_w2_aud_pw2 {
 | |
| 				nvidia,pins = "gpio_w2_aud_pw2";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			gpio_w3_aud_pw3 {
 | |
| 				nvidia,pins = "gpio_w3_aud_pw3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			dap_mclk1_pw4 {
 | |
| 				nvidia,pins = "dap_mclk1_pw4";
 | |
| 				nvidia,function = "extperiph1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			clk2_out_pw5 {
 | |
| 				nvidia,pins = "clk2_out_pw5";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			uart3_txd_pw6 {
 | |
| 				nvidia,pins = "uart3_txd_pw6";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			uart3_rxd_pw7 {
 | |
| 				nvidia,pins = "uart3_rxd_pw7";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			dvfs_pwm_px0 {
 | |
| 				nvidia,pins = "dvfs_pwm_px0";
 | |
| 				nvidia,function = "cldvfs";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			gpio_x1_aud_px1 {
 | |
| 				nvidia,pins = "gpio_x1_aud_px1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			dvfs_clk_px2 {
 | |
| 				nvidia,pins = "dvfs_clk_px2";
 | |
| 				nvidia,function = "cldvfs";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			gpio_x3_aud_px3 {
 | |
| 				nvidia,pins = "gpio_x3_aud_px3";
 | |
| 				nvidia,function = "rsvd4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			gpio_x4_aud_px4 {
 | |
| 				nvidia,pins = "gpio_x4_aud_px4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			gpio_x5_aud_px5 {
 | |
| 				nvidia,pins = "gpio_x5_aud_px5";
 | |
| 				nvidia,function = "rsvd4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			gpio_x6_aud_px6 {
 | |
| 				nvidia,pins = "gpio_x6_aud_px6";
 | |
| 				nvidia,function = "gmi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			gpio_x7_aud_px7 {
 | |
| 				nvidia,pins = "gpio_x7_aud_px7";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			ulpi_clk_py0 {
 | |
| 				nvidia,pins = "ulpi_clk_py0";
 | |
| 				nvidia,function = "spi1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			ulpi_dir_py1 {
 | |
| 				nvidia,pins = "ulpi_dir_py1";
 | |
| 				nvidia,function = "spi1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			ulpi_nxt_py2 {
 | |
| 				nvidia,pins = "ulpi_nxt_py2";
 | |
| 				nvidia,function = "spi1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			ulpi_stp_py3 {
 | |
| 				nvidia,pins = "ulpi_stp_py3";
 | |
| 				nvidia,function = "spi1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			sdmmc1_dat3_py4 {
 | |
| 				nvidia,pins = "sdmmc1_dat3_py4";
 | |
| 				nvidia,function = "sdmmc1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc1_dat2_py5 {
 | |
| 				nvidia,pins = "sdmmc1_dat2_py5";
 | |
| 				nvidia,function = "sdmmc1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc1_dat1_py6 {
 | |
| 				nvidia,pins = "sdmmc1_dat1_py6";
 | |
| 				nvidia,function = "sdmmc1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc1_dat0_py7 {
 | |
| 				nvidia,pins = "sdmmc1_dat0_py7";
 | |
| 				nvidia,function = "sdmmc1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc1_clk_pz0 {
 | |
| 				nvidia,pins = "sdmmc1_clk_pz0";
 | |
| 				nvidia,function = "sdmmc1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc1_cmd_pz1 {
 | |
| 				nvidia,pins = "sdmmc1_cmd_pz1";
 | |
| 				nvidia,function = "sdmmc1";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			pwr_i2c_scl_pz6 {
 | |
| 				nvidia,pins = "pwr_i2c_scl_pz6";
 | |
| 				nvidia,function = "i2cpwr";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			pwr_i2c_sda_pz7 {
 | |
| 				nvidia,pins = "pwr_i2c_sda_pz7";
 | |
| 				nvidia,function = "i2cpwr";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc4_dat0_paa0 {
 | |
| 				nvidia,pins = "sdmmc4_dat0_paa0";
 | |
| 				nvidia,function = "sdmmc4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc4_dat1_paa1 {
 | |
| 				nvidia,pins = "sdmmc4_dat1_paa1";
 | |
| 				nvidia,function = "sdmmc4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc4_dat2_paa2 {
 | |
| 				nvidia,pins = "sdmmc4_dat2_paa2";
 | |
| 				nvidia,function = "sdmmc4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc4_dat3_paa3 {
 | |
| 				nvidia,pins = "sdmmc4_dat3_paa3";
 | |
| 				nvidia,function = "sdmmc4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc4_dat4_paa4 {
 | |
| 				nvidia,pins = "sdmmc4_dat4_paa4";
 | |
| 				nvidia,function = "sdmmc4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc4_dat5_paa5 {
 | |
| 				nvidia,pins = "sdmmc4_dat5_paa5";
 | |
| 				nvidia,function = "sdmmc4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc4_dat6_paa6 {
 | |
| 				nvidia,pins = "sdmmc4_dat6_paa6";
 | |
| 				nvidia,function = "sdmmc4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc4_dat7_paa7 {
 | |
| 				nvidia,pins = "sdmmc4_dat7_paa7";
 | |
| 				nvidia,function = "sdmmc4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			pbb0 {
 | |
| 				nvidia,pins = "pbb0";
 | |
| 				nvidia,function = "vgp6";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			cam_i2c_scl_pbb1 {
 | |
| 				nvidia,pins = "cam_i2c_scl_pbb1";
 | |
| 				nvidia,function = "i2c3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			cam_i2c_sda_pbb2 {
 | |
| 				nvidia,pins = "cam_i2c_sda_pbb2";
 | |
| 				nvidia,function = "i2c3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			pbb3 {
 | |
| 				nvidia,pins = "pbb3";
 | |
| 				nvidia,function = "vgp3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pbb4 {
 | |
| 				nvidia,pins = "pbb4";
 | |
| 				nvidia,function = "vgp4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pbb5 {
 | |
| 				nvidia,pins = "pbb5";
 | |
| 				nvidia,function = "rsvd3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pbb6 {
 | |
| 				nvidia,pins = "pbb6";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pbb7 {
 | |
| 				nvidia,pins = "pbb7";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			cam_mclk_pcc0 {
 | |
| 				nvidia,pins = "cam_mclk_pcc0";
 | |
| 				nvidia,function = "vi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pcc1 {
 | |
| 				nvidia,pins = "pcc1";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pcc2 {
 | |
| 				nvidia,pins = "pcc2";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			sdmmc4_clk_pcc4 {
 | |
| 				nvidia,pins = "sdmmc4_clk_pcc4";
 | |
| 				nvidia,function = "sdmmc4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			clk2_req_pcc5 {
 | |
| 				nvidia,pins = "clk2_req_pcc5";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pex_l0_rst_n_pdd1 {
 | |
| 				nvidia,pins = "pex_l0_rst_n_pdd1";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pex_l0_clkreq_n_pdd2 {
 | |
| 				nvidia,pins = "pex_l0_clkreq_n_pdd2";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pex_wake_n_pdd3 {
 | |
| 				nvidia,pins = "pex_wake_n_pdd3";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pex_l1_rst_n_pdd5 {
 | |
| 				nvidia,pins = "pex_l1_rst_n_pdd5";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pex_l1_clkreq_n_pdd6 {
 | |
| 				nvidia,pins = "pex_l1_clkreq_n_pdd6";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			clk3_out_pee0 {
 | |
| 				nvidia,pins = "clk3_out_pee0";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			clk3_req_pee1 {
 | |
| 				nvidia,pins = "clk3_req_pee1";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			dap_mclk1_req_pee2 {
 | |
| 				nvidia,pins = "dap_mclk1_req_pee2";
 | |
| 				nvidia,function = "rsvd4";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			hdmi_cec_pee3 {
 | |
| 				nvidia,pins = "hdmi_cec_pee3";
 | |
| 				nvidia,function = "cec";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			sdmmc3_clk_lb_out_pee4 {
 | |
| 				nvidia,pins = "sdmmc3_clk_lb_out_pee4";
 | |
| 				nvidia,function = "sdmmc3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			sdmmc3_clk_lb_in_pee5 {
 | |
| 				nvidia,pins = "sdmmc3_clk_lb_in_pee5";
 | |
| 				nvidia,function = "sdmmc3";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			dp_hpd_pff0 {
 | |
| 				nvidia,pins = "dp_hpd_pff0";
 | |
| 				nvidia,function = "dp";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			usb_vbus_en2_pff1 {
 | |
| 				nvidia,pins = "usb_vbus_en2_pff1";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pff2 {
 | |
| 				nvidia,pins = "pff2";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			core_pwr_req {
 | |
| 				nvidia,pins = "core_pwr_req";
 | |
| 				nvidia,function = "pwron";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			cpu_pwr_req {
 | |
| 				nvidia,pins = "cpu_pwr_req";
 | |
| 				nvidia,function = "cpu";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			pwr_int_n {
 | |
| 				nvidia,pins = "pwr_int_n";
 | |
| 				nvidia,function = "pmi";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			reset_out_n {
 | |
| 				nvidia,pins = "reset_out_n";
 | |
| 				nvidia,function = "reset_out_n";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			owr {
 | |
| 				nvidia,pins = "owr";
 | |
| 				nvidia,function = "rsvd2";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 			clk_32k_in {
 | |
| 				nvidia,pins = "clk_32k_in";
 | |
| 				nvidia,function = "clk";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 | |
| 			};
 | |
| 			jtag_rtck {
 | |
| 				nvidia,pins = "jtag_rtck";
 | |
| 				nvidia,function = "rtck";
 | |
| 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 | |
| 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 | |
| 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 | |
| 			};
 | |
| 		};
 | |
| 	};
 | |
| };
 |