ef85d057a6
When targeting MIPSr6 or higher make use of a compact branch in LL/SC loops, preventing the insertion of a delay slot nop that only serves to waste space. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: linux-kernel@vger.kernel.org
44 lines
1005 B
C
44 lines
1005 B
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Macros for 32/64-bit neutral inline assembler
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*/
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#ifndef __ASM_LLSC_H
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#define __ASM_LLSC_H
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#include <asm/isa-rev.h>
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#if _MIPS_SZLONG == 32
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#define SZLONG_LOG 5
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#define SZLONG_MASK 31UL
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#define __LL "ll "
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#define __SC "sc "
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#define __INS "ins "
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#define __EXT "ext "
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#elif _MIPS_SZLONG == 64
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#define SZLONG_LOG 6
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#define SZLONG_MASK 63UL
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#define __LL "lld "
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#define __SC "scd "
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#define __INS "dins "
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#define __EXT "dext "
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#endif
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/*
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* Using a branch-likely instruction to check the result of an sc instruction
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* works around a bug present in R10000 CPUs prior to revision 3.0 that could
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* cause ll-sc sequences to execute non-atomically.
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*/
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#if R10000_LLSC_WAR
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# define __SC_BEQZ "beqzl "
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#elif MIPS_ISA_REV >= 6
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# define __SC_BEQZ "beqzc "
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#else
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# define __SC_BEQZ "beqz "
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#endif
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#endif /* __ASM_LLSC_H */
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