Kan Liang cbea56395c perf/x86/cstate: Add Rocket Lake CPU support ... From the perspective of Intel cstate residency counters, Rocket Lake is the same as Ice Lake and Tiger Lake. Share the code with them. Update the comments for Rocket Lake. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20201019153528.13850-2-kan.liang@linux.intel.com		2020-10-29 11:00:40 +01:00
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amd	x86/events/amd/iommu: Fix sizeof mismatch	2020-10-03 16:30:56 +02:00
intel	perf/x86/cstate: Add Rocket Lake CPU support	2020-10-29 11:00:40 +01:00
zhaoxin	x86/perf: Fix a typo	2020-07-22 10:22:08 +02:00
core.c	perf/x86: Fix n_metric for cancelled txn	2020-10-06 15:18:17 +02:00
Kconfig	treewide: replace '---help---' in Kconfig files with 'help'	2020-06-14 01:57:21 +09:00
Makefile	perf/x86/rapl: Fix RAPL config variable bug	2020-06-02 11:52:56 +02:00
msr.c	perf/x86/msr: Add Jasper Lake support	2020-09-29 09:57:02 +02:00
perf_event.h	perf/core: Add support for PERF_SAMPLE_CODE_PAGE_SIZE	2020-10-29 11:00:39 +01:00
probe.c	perf/x86/rapl: Make perf_probe_msr() more robust and flexible	2020-05-28 07:58:55 +02:00
probe.h	perf/x86: Add MSR probe interface	2019-06-24 19:28:31 +02:00
rapl.c	perf/x86/rapl: Add AMD Fam19h RAPL support	2020-09-10 11:19:36 +02:00