01d6b95605
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
81 lines
2.4 KiB
C
81 lines
2.4 KiB
C
/*
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* Copyright 2012 Nouveau Community
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Martin Peres <martin.peres@labri.fr>
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* Ben Skeggs
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*/
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#include "nv04.h"
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static void
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gf100_bus_intr(struct nvkm_subdev *subdev)
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{
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struct nvkm_bus *bus = nvkm_bus(subdev);
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u32 stat = nv_rd32(bus, 0x001100) & nv_rd32(bus, 0x001140);
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if (stat & 0x0000000e) {
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u32 addr = nv_rd32(bus, 0x009084);
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u32 data = nv_rd32(bus, 0x009088);
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nv_error(bus, "MMIO %s of 0x%08x FAULT at 0x%06x [ %s%s%s]\n",
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(addr & 0x00000002) ? "write" : "read", data,
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(addr & 0x00fffffc),
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(stat & 0x00000002) ? "!ENGINE " : "",
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(stat & 0x00000004) ? "IBUS " : "",
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(stat & 0x00000008) ? "TIMEOUT " : "");
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nv_wr32(bus, 0x009084, 0x00000000);
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nv_wr32(bus, 0x001100, (stat & 0x0000000e));
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stat &= ~0x0000000e;
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}
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if (stat) {
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nv_error(bus, "unknown intr 0x%08x\n", stat);
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nv_mask(bus, 0x001140, stat, 0x00000000);
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}
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}
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static int
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gf100_bus_init(struct nvkm_object *object)
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{
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struct nvkm_bus *bus = (void *)object;
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int ret;
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ret = nvkm_bus_init(bus);
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if (ret)
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return ret;
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nv_wr32(bus, 0x001100, 0xffffffff);
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nv_wr32(bus, 0x001140, 0x0000000e);
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return 0;
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}
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struct nvkm_oclass *
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gf100_bus_oclass = &(struct nv04_bus_impl) {
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.base.handle = NV_SUBDEV(BUS, 0xc0),
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.base.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv04_bus_ctor,
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.dtor = _nvkm_bus_dtor,
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.init = gf100_bus_init,
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.fini = _nvkm_bus_fini,
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},
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.intr = gf100_bus_intr,
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}.base;
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