linux/drivers/gpu
Chris Wilson cb0d205e0f drm/i915: Reduce locking in gen8 IRQ handler
Similar in vain in reducing the number of unrequired spinlocks used for
execlist command submission (where the forcewake is required but
manually controlled), we know that the IRQ registers are outside of the
powerwell and so we can access them directly. Since we now have direct
access exported via I915_READ_FW/I915_WRITE_FW, lets put those to use in
the irq handlers as well.

In the process, reorder the execlist submission to happen as early as
possible.

v2: Restrict the untraced register mmio to just the GT path (i.e. the
hotpath for execlists)

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-04-10 10:33:32 +02:00
..
drm drm/i915: Reduce locking in gen8 IRQ handler 2015-04-10 10:33:32 +02:00
host1x gpu: host1x: Provide a proper struct bus_type 2015-01-27 10:09:14 +01:00
ipu-v3 gpu: ipu-v3: do not divide by zero if the pixel clock is too large 2015-02-23 17:18:59 +01:00
vga
Makefile gpu: host1x: Provide a proper struct bus_type 2015-01-27 10:09:14 +01:00