forked from Minki/linux
ca78d3173c
- Errata workarounds for Qualcomm's Falkor CPU - Qualcomm L2 Cache PMU driver - Qualcomm SMCCC firmware quirk - Support for DEBUG_VIRTUAL - CPU feature detection for userspace via MRS emulation - Preliminary work for the Statistical Profiling Extension - Misc cleanups and non-critical fixes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCgAGBQJYpIxqAAoJELescNyEwWM0xdwH/AsTYAXPZDMdRnrQUyV0Fd2H /9pMzww6dHXEmCMKkImf++otUD6S+gTCJTsj7kEAXT5sZzLk27std5lsW7R9oPjc bGQMalZy+ovLR1gJ6v072seM3In4xph/qAYOpD8Q0AfYCLHjfMMArQfoLa8Esgru eSsrAgzVAkrK7XHi3sYycUjr9Hac9tvOOuQ3SaZkDz4MfFIbI4b43+c1SCF7wgT9 tQUHLhhxzGmgxjViI2lLYZuBWsIWsE+algvOe1qocvA9JEIXF+W8NeOuCjdL8WwX 3aoqYClC+qD/9+/skShFv5gM5fo0/IweLTUNIHADXpB6OkCYDyg+sxNM+xnEWQU= =YrPg -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Will Deacon: - Errata workarounds for Qualcomm's Falkor CPU - Qualcomm L2 Cache PMU driver - Qualcomm SMCCC firmware quirk - Support for DEBUG_VIRTUAL - CPU feature detection for userspace via MRS emulation - Preliminary work for the Statistical Profiling Extension - Misc cleanups and non-critical fixes * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (74 commits) arm64/kprobes: consistently handle MRS/MSR with XZR arm64: cpufeature: correctly handle MRS to XZR arm64: traps: correctly handle MRS/MSR with XZR arm64: ptrace: add XZR-safe regs accessors arm64: include asm/assembler.h in entry-ftrace.S arm64: fix warning about swapper_pg_dir overflow arm64: Work around Falkor erratum 1003 arm64: head.S: Enable EL1 (host) access to SPE when entered at EL2 arm64: arch_timer: document Hisilicon erratum 161010101 arm64: use is_vmalloc_addr arm64: use linux/sizes.h for constants arm64: uaccess: consistently check object sizes perf: add qcom l2 cache perf events driver arm64: remove wrong CONFIG_PROC_SYSCTL ifdef ARM: smccc: Update HVC comment to describe new quirk parameter arm64: do not trace atomic operations ACPI/IORT: Fix the error return code in iort_add_smmu_platform_device() ACPI/IORT: Fix iort_node_get_id() mapping entries indexing arm64: mm: enable CONFIG_HOLES_IN_ZONE for NUMA perf: xgene: Include module.h ...
531 lines
12 KiB
C
531 lines
12 KiB
C
/*
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* arch/arm64/kernel/topology.c
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*
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* Copyright (C) 2011,2013,2014 Linaro Limited.
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*
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* Based on the arm32 version written by Vincent Guittot in turn based on
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* arch/sh/kernel/topology.c
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/acpi.h>
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#include <linux/cpu.h>
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#include <linux/cpumask.h>
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#include <linux/init.h>
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#include <linux/percpu.h>
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#include <linux/node.h>
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#include <linux/nodemask.h>
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#include <linux/of.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/cpufreq.h>
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#include <asm/cpu.h>
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#include <asm/cputype.h>
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#include <asm/topology.h>
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static DEFINE_PER_CPU(unsigned long, cpu_scale) = SCHED_CAPACITY_SCALE;
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static DEFINE_MUTEX(cpu_scale_mutex);
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unsigned long arch_scale_cpu_capacity(struct sched_domain *sd, int cpu)
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{
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return per_cpu(cpu_scale, cpu);
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}
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static void set_capacity_scale(unsigned int cpu, unsigned long capacity)
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{
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per_cpu(cpu_scale, cpu) = capacity;
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}
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static ssize_t cpu_capacity_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct cpu *cpu = container_of(dev, struct cpu, dev);
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return sprintf(buf, "%lu\n",
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arch_scale_cpu_capacity(NULL, cpu->dev.id));
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}
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static ssize_t cpu_capacity_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf,
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size_t count)
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{
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struct cpu *cpu = container_of(dev, struct cpu, dev);
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int this_cpu = cpu->dev.id, i;
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unsigned long new_capacity;
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ssize_t ret;
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if (count) {
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ret = kstrtoul(buf, 0, &new_capacity);
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if (ret)
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return ret;
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if (new_capacity > SCHED_CAPACITY_SCALE)
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return -EINVAL;
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mutex_lock(&cpu_scale_mutex);
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for_each_cpu(i, &cpu_topology[this_cpu].core_sibling)
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set_capacity_scale(i, new_capacity);
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mutex_unlock(&cpu_scale_mutex);
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}
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return count;
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}
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static DEVICE_ATTR_RW(cpu_capacity);
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static int register_cpu_capacity_sysctl(void)
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{
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int i;
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struct device *cpu;
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for_each_possible_cpu(i) {
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cpu = get_cpu_device(i);
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if (!cpu) {
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pr_err("%s: too early to get CPU%d device!\n",
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__func__, i);
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continue;
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}
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device_create_file(cpu, &dev_attr_cpu_capacity);
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}
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return 0;
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}
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subsys_initcall(register_cpu_capacity_sysctl);
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static u32 capacity_scale;
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static u32 *raw_capacity;
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static bool cap_parsing_failed;
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static void __init parse_cpu_capacity(struct device_node *cpu_node, int cpu)
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{
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int ret;
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u32 cpu_capacity;
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if (cap_parsing_failed)
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return;
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ret = of_property_read_u32(cpu_node,
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"capacity-dmips-mhz",
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&cpu_capacity);
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if (!ret) {
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if (!raw_capacity) {
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raw_capacity = kcalloc(num_possible_cpus(),
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sizeof(*raw_capacity),
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GFP_KERNEL);
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if (!raw_capacity) {
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pr_err("cpu_capacity: failed to allocate memory for raw capacities\n");
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cap_parsing_failed = true;
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return;
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}
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}
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capacity_scale = max(cpu_capacity, capacity_scale);
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raw_capacity[cpu] = cpu_capacity;
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pr_debug("cpu_capacity: %s cpu_capacity=%u (raw)\n",
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cpu_node->full_name, raw_capacity[cpu]);
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} else {
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if (raw_capacity) {
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pr_err("cpu_capacity: missing %s raw capacity\n",
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cpu_node->full_name);
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pr_err("cpu_capacity: partial information: fallback to 1024 for all CPUs\n");
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}
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cap_parsing_failed = true;
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kfree(raw_capacity);
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}
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}
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static void normalize_cpu_capacity(void)
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{
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u64 capacity;
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int cpu;
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if (!raw_capacity || cap_parsing_failed)
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return;
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pr_debug("cpu_capacity: capacity_scale=%u\n", capacity_scale);
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mutex_lock(&cpu_scale_mutex);
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for_each_possible_cpu(cpu) {
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pr_debug("cpu_capacity: cpu=%d raw_capacity=%u\n",
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cpu, raw_capacity[cpu]);
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capacity = (raw_capacity[cpu] << SCHED_CAPACITY_SHIFT)
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/ capacity_scale;
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set_capacity_scale(cpu, capacity);
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pr_debug("cpu_capacity: CPU%d cpu_capacity=%lu\n",
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cpu, arch_scale_cpu_capacity(NULL, cpu));
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}
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mutex_unlock(&cpu_scale_mutex);
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}
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#ifdef CONFIG_CPU_FREQ
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static cpumask_var_t cpus_to_visit;
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static bool cap_parsing_done;
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static void parsing_done_workfn(struct work_struct *work);
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static DECLARE_WORK(parsing_done_work, parsing_done_workfn);
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static int
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init_cpu_capacity_callback(struct notifier_block *nb,
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unsigned long val,
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void *data)
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{
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struct cpufreq_policy *policy = data;
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int cpu;
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if (cap_parsing_failed || cap_parsing_done)
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return 0;
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switch (val) {
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case CPUFREQ_NOTIFY:
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pr_debug("cpu_capacity: init cpu capacity for CPUs [%*pbl] (to_visit=%*pbl)\n",
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cpumask_pr_args(policy->related_cpus),
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cpumask_pr_args(cpus_to_visit));
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cpumask_andnot(cpus_to_visit,
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cpus_to_visit,
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policy->related_cpus);
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for_each_cpu(cpu, policy->related_cpus) {
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raw_capacity[cpu] = arch_scale_cpu_capacity(NULL, cpu) *
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policy->cpuinfo.max_freq / 1000UL;
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capacity_scale = max(raw_capacity[cpu], capacity_scale);
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}
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if (cpumask_empty(cpus_to_visit)) {
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normalize_cpu_capacity();
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kfree(raw_capacity);
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pr_debug("cpu_capacity: parsing done\n");
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cap_parsing_done = true;
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schedule_work(&parsing_done_work);
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}
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}
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return 0;
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}
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static struct notifier_block init_cpu_capacity_notifier = {
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.notifier_call = init_cpu_capacity_callback,
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};
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static int __init register_cpufreq_notifier(void)
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{
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/*
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* on ACPI-based systems we need to use the default cpu capacity
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* until we have the necessary code to parse the cpu capacity, so
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* skip registering cpufreq notifier.
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*/
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if (!acpi_disabled || cap_parsing_failed)
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return -EINVAL;
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if (!alloc_cpumask_var(&cpus_to_visit, GFP_KERNEL)) {
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pr_err("cpu_capacity: failed to allocate memory for cpus_to_visit\n");
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return -ENOMEM;
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}
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cpumask_copy(cpus_to_visit, cpu_possible_mask);
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return cpufreq_register_notifier(&init_cpu_capacity_notifier,
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CPUFREQ_POLICY_NOTIFIER);
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}
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core_initcall(register_cpufreq_notifier);
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static void parsing_done_workfn(struct work_struct *work)
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{
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cpufreq_unregister_notifier(&init_cpu_capacity_notifier,
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CPUFREQ_POLICY_NOTIFIER);
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}
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#else
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static int __init free_raw_capacity(void)
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{
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kfree(raw_capacity);
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return 0;
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}
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core_initcall(free_raw_capacity);
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#endif
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static int __init get_cpu_for_node(struct device_node *node)
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{
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struct device_node *cpu_node;
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int cpu;
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cpu_node = of_parse_phandle(node, "cpu", 0);
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if (!cpu_node)
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return -1;
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for_each_possible_cpu(cpu) {
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if (of_get_cpu_node(cpu, NULL) == cpu_node) {
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parse_cpu_capacity(cpu_node, cpu);
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of_node_put(cpu_node);
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return cpu;
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}
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}
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pr_crit("Unable to find CPU node for %s\n", cpu_node->full_name);
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of_node_put(cpu_node);
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return -1;
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}
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static int __init parse_core(struct device_node *core, int cluster_id,
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int core_id)
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{
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char name[10];
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bool leaf = true;
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int i = 0;
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int cpu;
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struct device_node *t;
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do {
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snprintf(name, sizeof(name), "thread%d", i);
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t = of_get_child_by_name(core, name);
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if (t) {
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leaf = false;
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cpu = get_cpu_for_node(t);
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if (cpu >= 0) {
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cpu_topology[cpu].cluster_id = cluster_id;
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cpu_topology[cpu].core_id = core_id;
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cpu_topology[cpu].thread_id = i;
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} else {
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pr_err("%s: Can't get CPU for thread\n",
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t->full_name);
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of_node_put(t);
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return -EINVAL;
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}
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of_node_put(t);
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}
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i++;
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} while (t);
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cpu = get_cpu_for_node(core);
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if (cpu >= 0) {
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if (!leaf) {
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pr_err("%s: Core has both threads and CPU\n",
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core->full_name);
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return -EINVAL;
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}
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cpu_topology[cpu].cluster_id = cluster_id;
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cpu_topology[cpu].core_id = core_id;
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} else if (leaf) {
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pr_err("%s: Can't get CPU for leaf core\n", core->full_name);
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return -EINVAL;
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}
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return 0;
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}
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static int __init parse_cluster(struct device_node *cluster, int depth)
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{
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char name[10];
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bool leaf = true;
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bool has_cores = false;
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struct device_node *c;
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static int cluster_id __initdata;
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int core_id = 0;
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int i, ret;
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/*
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* First check for child clusters; we currently ignore any
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* information about the nesting of clusters and present the
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* scheduler with a flat list of them.
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*/
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i = 0;
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do {
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snprintf(name, sizeof(name), "cluster%d", i);
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c = of_get_child_by_name(cluster, name);
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if (c) {
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leaf = false;
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ret = parse_cluster(c, depth + 1);
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of_node_put(c);
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if (ret != 0)
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return ret;
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}
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i++;
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} while (c);
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/* Now check for cores */
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i = 0;
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do {
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snprintf(name, sizeof(name), "core%d", i);
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c = of_get_child_by_name(cluster, name);
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if (c) {
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has_cores = true;
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if (depth == 0) {
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pr_err("%s: cpu-map children should be clusters\n",
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c->full_name);
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of_node_put(c);
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return -EINVAL;
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}
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if (leaf) {
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ret = parse_core(c, cluster_id, core_id++);
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} else {
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pr_err("%s: Non-leaf cluster with core %s\n",
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cluster->full_name, name);
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ret = -EINVAL;
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}
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of_node_put(c);
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if (ret != 0)
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return ret;
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}
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i++;
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} while (c);
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if (leaf && !has_cores)
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pr_warn("%s: empty cluster\n", cluster->full_name);
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if (leaf)
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cluster_id++;
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return 0;
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}
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static int __init parse_dt_topology(void)
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{
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struct device_node *cn, *map;
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int ret = 0;
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int cpu;
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cn = of_find_node_by_path("/cpus");
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if (!cn) {
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pr_err("No CPU information found in DT\n");
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return 0;
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}
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|
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/*
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* When topology is provided cpu-map is essentially a root
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* cluster with restricted subnodes.
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*/
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map = of_get_child_by_name(cn, "cpu-map");
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if (!map) {
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cap_parsing_failed = true;
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goto out;
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}
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ret = parse_cluster(map, 0);
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if (ret != 0)
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goto out_map;
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normalize_cpu_capacity();
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/*
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* Check that all cores are in the topology; the SMP code will
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* only mark cores described in the DT as possible.
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*/
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for_each_possible_cpu(cpu)
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if (cpu_topology[cpu].cluster_id == -1)
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ret = -EINVAL;
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out_map:
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of_node_put(map);
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out:
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of_node_put(cn);
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return ret;
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}
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|
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/*
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* cpu topology table
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*/
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struct cpu_topology cpu_topology[NR_CPUS];
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EXPORT_SYMBOL_GPL(cpu_topology);
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|
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const struct cpumask *cpu_coregroup_mask(int cpu)
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{
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return &cpu_topology[cpu].core_sibling;
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}
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|
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static void update_siblings_masks(unsigned int cpuid)
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{
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struct cpu_topology *cpu_topo, *cpuid_topo = &cpu_topology[cpuid];
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int cpu;
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|
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/* update core and thread sibling masks */
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for_each_possible_cpu(cpu) {
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cpu_topo = &cpu_topology[cpu];
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|
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if (cpuid_topo->cluster_id != cpu_topo->cluster_id)
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continue;
|
|
|
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cpumask_set_cpu(cpuid, &cpu_topo->core_sibling);
|
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if (cpu != cpuid)
|
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cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);
|
|
|
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if (cpuid_topo->core_id != cpu_topo->core_id)
|
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continue;
|
|
|
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cpumask_set_cpu(cpuid, &cpu_topo->thread_sibling);
|
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if (cpu != cpuid)
|
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cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);
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}
|
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}
|
|
|
|
void store_cpu_topology(unsigned int cpuid)
|
|
{
|
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struct cpu_topology *cpuid_topo = &cpu_topology[cpuid];
|
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u64 mpidr;
|
|
|
|
if (cpuid_topo->cluster_id != -1)
|
|
goto topology_populated;
|
|
|
|
mpidr = read_cpuid_mpidr();
|
|
|
|
/* Uniprocessor systems can rely on default topology values */
|
|
if (mpidr & MPIDR_UP_BITMASK)
|
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return;
|
|
|
|
/* Create cpu topology mapping based on MPIDR. */
|
|
if (mpidr & MPIDR_MT_BITMASK) {
|
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/* Multiprocessor system : Multi-threads per core */
|
|
cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
|
|
cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
|
|
cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 2) |
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MPIDR_AFFINITY_LEVEL(mpidr, 3) << 8;
|
|
} else {
|
|
/* Multiprocessor system : Single-thread per core */
|
|
cpuid_topo->thread_id = -1;
|
|
cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
|
|
cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 1) |
|
|
MPIDR_AFFINITY_LEVEL(mpidr, 2) << 8 |
|
|
MPIDR_AFFINITY_LEVEL(mpidr, 3) << 16;
|
|
}
|
|
|
|
pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n",
|
|
cpuid, cpuid_topo->cluster_id, cpuid_topo->core_id,
|
|
cpuid_topo->thread_id, mpidr);
|
|
|
|
topology_populated:
|
|
update_siblings_masks(cpuid);
|
|
}
|
|
|
|
static void __init reset_cpu_topology(void)
|
|
{
|
|
unsigned int cpu;
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
struct cpu_topology *cpu_topo = &cpu_topology[cpu];
|
|
|
|
cpu_topo->thread_id = -1;
|
|
cpu_topo->core_id = 0;
|
|
cpu_topo->cluster_id = -1;
|
|
|
|
cpumask_clear(&cpu_topo->core_sibling);
|
|
cpumask_set_cpu(cpu, &cpu_topo->core_sibling);
|
|
cpumask_clear(&cpu_topo->thread_sibling);
|
|
cpumask_set_cpu(cpu, &cpu_topo->thread_sibling);
|
|
}
|
|
}
|
|
|
|
void __init init_cpu_topology(void)
|
|
{
|
|
reset_cpu_topology();
|
|
|
|
/*
|
|
* Discard anything that was parsed if we hit an error so we
|
|
* don't use partial information.
|
|
*/
|
|
if (of_have_populated_dt() && parse_dt_topology())
|
|
reset_cpu_topology();
|
|
}
|