7457cf0254
This patch adds get_max_sustainable_clock function for smu11. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
90 lines
2.8 KiB
C
90 lines
2.8 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __SMU_V11_0_H__
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#define __SMU_V11_0_H__
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#include "amdgpu_smu.h"
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/* MP Apertures */
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#define MP0_Public 0x03800000
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#define MP0_SRAM 0x03900000
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#define MP1_Public 0x03b00000
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#define MP1_SRAM 0x03c00004
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/* address block */
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#define smnMP1_FIRMWARE_FLAGS 0x3010024
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#define smnMP0_FW_INTF 0x30101c0
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#define smnMP1_PUB_CTRL 0x3010b14
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struct smu_11_0_max_sustainable_clocks {
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uint32_t display_clock;
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uint32_t phy_clock;
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uint32_t pixel_clock;
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uint32_t uclock;
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uint32_t dcef_clock;
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uint32_t soc_clock;
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};
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struct smu_11_0_dpm_table {
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uint32_t min; /* MHz */
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uint32_t max; /* MHz */
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};
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struct smu_11_0_dpm_tables {
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struct smu_11_0_dpm_table soc_table;
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struct smu_11_0_dpm_table gfx_table;
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struct smu_11_0_dpm_table uclk_table;
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struct smu_11_0_dpm_table eclk_table;
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struct smu_11_0_dpm_table vclk_table;
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struct smu_11_0_dpm_table dclk_table;
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struct smu_11_0_dpm_table dcef_table;
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struct smu_11_0_dpm_table pixel_table;
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struct smu_11_0_dpm_table display_table;
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struct smu_11_0_dpm_table phy_table;
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struct smu_11_0_dpm_table fclk_table;
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};
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struct smu_11_0_dpm_context {
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struct smu_11_0_dpm_tables dpm_tables;
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uint32_t workload_policy_mask;
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uint32_t dcef_min_ds_clk;
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};
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enum smu_11_0_power_state {
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SMU_11_0_POWER_STATE__D0 = 0,
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SMU_11_0_POWER_STATE__D1,
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SMU_11_0_POWER_STATE__D3, /* Sleep*/
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SMU_11_0_POWER_STATE__D4, /* Hibernate*/
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SMU_11_0_POWER_STATE__D5, /* Power off*/
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};
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struct smu_11_0_power_context {
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uint32_t power_source;
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uint8_t in_power_limit_boost_mode;
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enum smu_11_0_power_state power_state;
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};
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void smu_v11_0_set_smu_funcs(struct smu_context *smu);
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#endif
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