The 88E6352 family supports Energy Detect and has one bit for Sense and one bit for periodically transmit NLP (Energy Detect+TM). The 88E6390 family adds another bit to distinguish Auto or SW wake-up. Chips supporting EEE all have an EEE Enabled bit in the Port Status Register. This patch adds new ops for the PHY Energy Detect accesses. This also allows us to get rid of the MV88E6XXX_FLAG_EEE flag. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
345 lines
7.9 KiB
C
345 lines
7.9 KiB
C
/*
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* Marvell 88e6xxx Ethernet switch PHY and PPU support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2017 Andrew Lunn <andrew@lunn.ch>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/mdio.h>
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#include <linux/module.h>
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#include "chip.h"
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#include "phy.h"
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int mv88e6165_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
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int addr, int reg, u16 *val)
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{
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return mv88e6xxx_read(chip, addr, reg, val);
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}
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int mv88e6165_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
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int addr, int reg, u16 val)
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{
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return mv88e6xxx_write(chip, addr, reg, val);
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}
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int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy, int reg, u16 *val)
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{
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int addr = phy; /* PHY devices addresses start at 0x0 */
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struct mii_bus *bus;
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bus = mv88e6xxx_default_mdio_bus(chip);
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if (!bus)
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return -EOPNOTSUPP;
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if (!chip->info->ops->phy_read)
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return -EOPNOTSUPP;
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return chip->info->ops->phy_read(chip, bus, addr, reg, val);
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}
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int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, int reg, u16 val)
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{
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int addr = phy; /* PHY devices addresses start at 0x0 */
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struct mii_bus *bus;
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bus = mv88e6xxx_default_mdio_bus(chip);
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if (!bus)
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return -EOPNOTSUPP;
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if (!chip->info->ops->phy_write)
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return -EOPNOTSUPP;
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return chip->info->ops->phy_write(chip, bus, addr, reg, val);
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}
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static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
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{
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return mv88e6xxx_phy_write(chip, phy, MV88E6XXX_PHY_PAGE, page);
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}
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static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
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{
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int err;
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/* Restore PHY page Copper 0x0 for access via the registered
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* MDIO bus
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*/
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err = mv88e6xxx_phy_write(chip, phy, MV88E6XXX_PHY_PAGE,
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MV88E6XXX_PHY_PAGE_COPPER);
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if (unlikely(err)) {
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dev_err(chip->dev,
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"failed to restore PHY %d page Copper (%d)\n",
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phy, err);
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}
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}
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int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
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u8 page, int reg, u16 *val)
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{
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int err;
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/* There is no paging for registers 22 */
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if (reg == MV88E6XXX_PHY_PAGE)
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return -EINVAL;
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err = mv88e6xxx_phy_page_get(chip, phy, page);
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if (!err) {
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err = mv88e6xxx_phy_read(chip, phy, reg, val);
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mv88e6xxx_phy_page_put(chip, phy);
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}
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return err;
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}
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int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
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u8 page, int reg, u16 val)
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{
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int err;
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/* There is no paging for registers 22 */
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if (reg == MV88E6XXX_PHY_PAGE)
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return -EINVAL;
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err = mv88e6xxx_phy_page_get(chip, phy, page);
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if (!err) {
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err = mv88e6xxx_phy_write(chip, phy, MV88E6XXX_PHY_PAGE, page);
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mv88e6xxx_phy_page_put(chip, phy);
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}
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return err;
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}
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static int mv88e6xxx_phy_ppu_disable(struct mv88e6xxx_chip *chip)
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{
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if (!chip->info->ops->ppu_disable)
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return 0;
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return chip->info->ops->ppu_disable(chip);
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}
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static int mv88e6xxx_phy_ppu_enable(struct mv88e6xxx_chip *chip)
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{
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if (!chip->info->ops->ppu_enable)
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return 0;
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return chip->info->ops->ppu_enable(chip);
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}
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static void mv88e6xxx_phy_ppu_reenable_work(struct work_struct *ugly)
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{
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struct mv88e6xxx_chip *chip;
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chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
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mutex_lock(&chip->reg_lock);
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if (mutex_trylock(&chip->ppu_mutex)) {
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if (mv88e6xxx_phy_ppu_enable(chip) == 0)
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chip->ppu_disabled = 0;
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mutex_unlock(&chip->ppu_mutex);
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}
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mutex_unlock(&chip->reg_lock);
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}
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static void mv88e6xxx_phy_ppu_reenable_timer(unsigned long _ps)
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{
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struct mv88e6xxx_chip *chip = (void *)_ps;
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schedule_work(&chip->ppu_work);
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}
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static int mv88e6xxx_phy_ppu_access_get(struct mv88e6xxx_chip *chip)
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{
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int ret;
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mutex_lock(&chip->ppu_mutex);
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/* If the PHY polling unit is enabled, disable it so that
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* we can access the PHY registers. If it was already
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* disabled, cancel the timer that is going to re-enable
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* it.
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*/
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if (!chip->ppu_disabled) {
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ret = mv88e6xxx_phy_ppu_disable(chip);
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if (ret < 0) {
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mutex_unlock(&chip->ppu_mutex);
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return ret;
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}
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chip->ppu_disabled = 1;
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} else {
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del_timer(&chip->ppu_timer);
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ret = 0;
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}
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return ret;
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}
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static void mv88e6xxx_phy_ppu_access_put(struct mv88e6xxx_chip *chip)
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{
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/* Schedule a timer to re-enable the PHY polling unit. */
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mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
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mutex_unlock(&chip->ppu_mutex);
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}
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static void mv88e6xxx_phy_ppu_state_init(struct mv88e6xxx_chip *chip)
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{
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mutex_init(&chip->ppu_mutex);
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INIT_WORK(&chip->ppu_work, mv88e6xxx_phy_ppu_reenable_work);
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setup_timer(&chip->ppu_timer, mv88e6xxx_phy_ppu_reenable_timer,
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(unsigned long)chip);
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}
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static void mv88e6xxx_phy_ppu_state_destroy(struct mv88e6xxx_chip *chip)
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{
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del_timer_sync(&chip->ppu_timer);
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}
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int mv88e6185_phy_ppu_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
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int addr, int reg, u16 *val)
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{
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int err;
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err = mv88e6xxx_phy_ppu_access_get(chip);
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if (!err) {
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err = mv88e6xxx_read(chip, addr, reg, val);
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mv88e6xxx_phy_ppu_access_put(chip);
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}
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return err;
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}
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int mv88e6185_phy_ppu_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
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int addr, int reg, u16 val)
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{
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int err;
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err = mv88e6xxx_phy_ppu_access_get(chip);
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if (!err) {
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err = mv88e6xxx_write(chip, addr, reg, val);
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mv88e6xxx_phy_ppu_access_put(chip);
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}
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return err;
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}
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void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
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{
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if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
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mv88e6xxx_phy_ppu_state_init(chip);
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}
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void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
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{
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if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
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mv88e6xxx_phy_ppu_state_destroy(chip);
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}
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int mv88e6xxx_phy_setup(struct mv88e6xxx_chip *chip)
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{
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return mv88e6xxx_phy_ppu_enable(chip);
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}
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/* Page 0, Register 16: Copper Specific Control Register 1 */
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int mv88e6352_phy_energy_detect_read(struct mv88e6xxx_chip *chip, int phy,
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struct ethtool_eee *eee)
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{
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u16 val;
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int err;
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err = mv88e6xxx_phy_read(chip, phy, MV88E6XXX_PHY_CSCTL1, &val);
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if (err)
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return err;
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val &= MV88E6352_PHY_CSCTL1_ENERGY_DETECT_MASK;
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eee->eee_enabled = false;
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eee->tx_lpi_enabled = false;
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switch (val) {
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case MV88E6352_PHY_CSCTL1_ENERGY_DETECT_SENSE_NLP:
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eee->tx_lpi_enabled = true;
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/* fall through... */
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case MV88E6352_PHY_CSCTL1_ENERGY_DETECT_SENSE_RCV:
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eee->eee_enabled = true;
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}
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return 0;
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}
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int mv88e6352_phy_energy_detect_write(struct mv88e6xxx_chip *chip, int phy,
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struct ethtool_eee *eee)
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{
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u16 val;
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int err;
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err = mv88e6xxx_phy_read(chip, phy, MV88E6XXX_PHY_CSCTL1, &val);
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if (err)
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return err;
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val &= ~MV88E6352_PHY_CSCTL1_ENERGY_DETECT_MASK;
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if (eee->eee_enabled)
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val |= MV88E6352_PHY_CSCTL1_ENERGY_DETECT_SENSE_RCV;
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if (eee->tx_lpi_enabled)
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val |= MV88E6352_PHY_CSCTL1_ENERGY_DETECT_SENSE_NLP;
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return mv88e6xxx_phy_write(chip, phy, MV88E6XXX_PHY_CSCTL1, val);
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}
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int mv88e6390_phy_energy_detect_read(struct mv88e6xxx_chip *chip, int phy,
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struct ethtool_eee *eee)
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{
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u16 val;
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int err;
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err = mv88e6xxx_phy_read(chip, phy, MV88E6XXX_PHY_CSCTL1, &val);
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if (err)
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return err;
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val &= MV88E6390_PHY_CSCTL1_ENERGY_DETECT_MASK;
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eee->eee_enabled = false;
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eee->tx_lpi_enabled = false;
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switch (val) {
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case MV88E6390_PHY_CSCTL1_ENERGY_DETECT_SENSE_NLP_AUTO:
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case MV88E6390_PHY_CSCTL1_ENERGY_DETECT_SENSE_NLP_SW:
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eee->tx_lpi_enabled = true;
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/* fall through... */
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case MV88E6390_PHY_CSCTL1_ENERGY_DETECT_SENSE_RCV_AUTO:
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case MV88E6390_PHY_CSCTL1_ENERGY_DETECT_SENSE_RCV_SW:
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eee->eee_enabled = true;
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}
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return 0;
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}
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int mv88e6390_phy_energy_detect_write(struct mv88e6xxx_chip *chip, int phy,
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struct ethtool_eee *eee)
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{
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u16 val;
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int err;
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err = mv88e6xxx_phy_read(chip, phy, MV88E6XXX_PHY_CSCTL1, &val);
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if (err)
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return err;
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val &= ~MV88E6390_PHY_CSCTL1_ENERGY_DETECT_MASK;
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if (eee->eee_enabled)
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val |= MV88E6390_PHY_CSCTL1_ENERGY_DETECT_SENSE_RCV_AUTO;
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if (eee->tx_lpi_enabled)
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val |= MV88E6390_PHY_CSCTL1_ENERGY_DETECT_SENSE_NLP_AUTO;
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return mv88e6xxx_phy_write(chip, phy, MV88E6XXX_PHY_CSCTL1, val);
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}
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