linux/drivers/gpu
Manasi Navare c92f47b5ec drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI
On Icelake platform, MG PHY is used when operating in DP alternate
mode or the legacy HDMI or DP modes. DDI Ports C, D, E, F are MG PHY
DDI ports on ICL.

This patch adds the necessary voltage swing programming related
register definitions and macros for MG PHY DDI ports.

v4 (from Paulo):
* Use _PORT instead of _PICK
* Change some mask names to our current coding standards
* Stay under 80 columns
v3:
* Rebase on new revision of patches
v2:
* Remove whitespaces in the #defines (Paulo)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180323172419.24911-4-paulo.r.zanoni@intel.com
2018-03-23 14:56:27 -07:00
..
drm drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI 2018-03-23 14:56:27 -07:00
host1x gpu: host1x: Use IOMMU groups 2017-12-21 14:52:36 +01:00
ipu-v3 gpu: ipu-v3: allow to build with COMPILE_TEST 2017-12-19 12:49:11 +01:00
vga vfs: do bulk POLL* -> EPOLL* replacement 2018-02-11 14:34:03 -08:00
Makefile