forked from Minki/linux
0a87a2db48
Conflicts: drivers/gpu/drm/i915/intel_runtime_pm.c Separate branch so that Takashi can also pull just this refactoring into sound-next. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
383 lines
12 KiB
C
383 lines
12 KiB
C
/*
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*
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* Copyright 2008 (c) Intel Corporation
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* Jesse Barnes <jbarnes@virtuousgeek.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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#include "intel_drv.h"
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#include "i915_reg.h"
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static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_WRITE8(index_port, reg);
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return I915_READ8(data_port);
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}
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static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_READ8(st01);
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I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
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return I915_READ8(VGA_AR_DATA_READ);
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}
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static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_READ8(st01);
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I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
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I915_WRITE8(VGA_AR_DATA_WRITE, val);
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}
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static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_WRITE8(index_port, reg);
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I915_WRITE8(data_port, val);
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}
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static void i915_save_vga(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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u16 cr_index, cr_data, st01;
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/* VGA state */
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dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
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dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
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dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
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dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));
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/* VGA color palette registers */
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dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
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/* MSR bits */
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dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
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if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
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cr_index = VGA_CR_INDEX_CGA;
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cr_data = VGA_CR_DATA_CGA;
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st01 = VGA_ST01_CGA;
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} else {
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cr_index = VGA_CR_INDEX_MDA;
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cr_data = VGA_CR_DATA_MDA;
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st01 = VGA_ST01_MDA;
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}
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/* CRT controller regs */
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i915_write_indexed(dev, cr_index, cr_data, 0x11,
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i915_read_indexed(dev, cr_index, cr_data, 0x11) &
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(~0x80));
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for (i = 0; i <= 0x24; i++)
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dev_priv->regfile.saveCR[i] =
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i915_read_indexed(dev, cr_index, cr_data, i);
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/* Make sure we don't turn off CR group 0 writes */
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dev_priv->regfile.saveCR[0x11] &= ~0x80;
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/* Attribute controller registers */
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I915_READ8(st01);
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dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
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for (i = 0; i <= 0x14; i++)
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dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
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I915_READ8(st01);
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I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
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I915_READ8(st01);
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/* Graphics controller registers */
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for (i = 0; i < 9; i++)
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dev_priv->regfile.saveGR[i] =
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i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
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dev_priv->regfile.saveGR[0x10] =
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i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
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dev_priv->regfile.saveGR[0x11] =
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i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
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dev_priv->regfile.saveGR[0x18] =
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i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
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/* Sequencer registers */
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for (i = 0; i < 8; i++)
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dev_priv->regfile.saveSR[i] =
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i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
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}
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static void i915_restore_vga(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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u16 cr_index, cr_data, st01;
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/* VGA state */
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I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL);
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I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
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I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
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I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
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POSTING_READ(VGA_PD);
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udelay(150);
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/* MSR bits */
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I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
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if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
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cr_index = VGA_CR_INDEX_CGA;
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cr_data = VGA_CR_DATA_CGA;
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st01 = VGA_ST01_CGA;
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} else {
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cr_index = VGA_CR_INDEX_MDA;
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cr_data = VGA_CR_DATA_MDA;
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st01 = VGA_ST01_MDA;
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}
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/* Sequencer registers, don't write SR07 */
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for (i = 0; i < 7; i++)
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i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
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dev_priv->regfile.saveSR[i]);
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/* CRT controller regs */
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/* Enable CR group 0 writes */
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i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
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for (i = 0; i <= 0x24; i++)
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i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);
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/* Graphics controller regs */
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for (i = 0; i < 9; i++)
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i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
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dev_priv->regfile.saveGR[i]);
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i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
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dev_priv->regfile.saveGR[0x10]);
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i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
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dev_priv->regfile.saveGR[0x11]);
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i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
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dev_priv->regfile.saveGR[0x18]);
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/* Attribute controller registers */
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I915_READ8(st01); /* switch back to index mode */
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for (i = 0; i <= 0x14; i++)
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i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
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I915_READ8(st01); /* switch back to index mode */
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I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20);
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I915_READ8(st01);
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/* VGA color palette registers */
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I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
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}
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static void i915_save_display(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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/* Display arbitration control */
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if (INTEL_INFO(dev)->gen <= 4)
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dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
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/* This is only meaningful in non-KMS mode */
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/* Don't regfile.save them in KMS mode */
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if (!drm_core_check_feature(dev, DRIVER_MODESET))
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i915_save_display_reg(dev);
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/* LVDS state */
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if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
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dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
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else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
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dev_priv->regfile.saveLVDS = I915_READ(LVDS);
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/* Panel power sequencer */
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if (HAS_PCH_SPLIT(dev)) {
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dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
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dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
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dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
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dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
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} else if (!IS_VALLEYVIEW(dev)) {
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dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
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dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
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dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
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dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
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}
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/* save FBC interval */
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if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
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dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
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if (!drm_core_check_feature(dev, DRIVER_MODESET))
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i915_save_vga(dev);
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}
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static void i915_restore_display(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 mask = 0xffffffff;
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/* Display arbitration */
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if (INTEL_INFO(dev)->gen <= 4)
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I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
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if (!drm_core_check_feature(dev, DRIVER_MODESET))
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i915_restore_display_reg(dev);
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if (drm_core_check_feature(dev, DRIVER_MODESET))
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mask = ~LVDS_PORT_EN;
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/* LVDS state */
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if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
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I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
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else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
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I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
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/* Panel power sequencer */
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if (HAS_PCH_SPLIT(dev)) {
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I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
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I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
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I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
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I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
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} else if (!IS_VALLEYVIEW(dev)) {
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I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
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I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
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I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
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I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
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}
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/* only restore FBC info on the platform that supports FBC*/
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intel_fbc_disable(dev);
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/* restore FBC interval */
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if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
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I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
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if (!drm_core_check_feature(dev, DRIVER_MODESET))
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i915_restore_vga(dev);
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else
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i915_redisable_vga(dev);
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}
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int i915_save_state(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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mutex_lock(&dev->struct_mutex);
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i915_save_display(dev);
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if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
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/* Interrupt state */
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if (HAS_PCH_SPLIT(dev)) {
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dev_priv->regfile.saveDEIER = I915_READ(DEIER);
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dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
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dev_priv->regfile.saveGTIER = I915_READ(GTIER);
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dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
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dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
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dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
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dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
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I915_READ(RSTDBYCTL);
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dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
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} else {
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dev_priv->regfile.saveIER = I915_READ(IER);
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dev_priv->regfile.saveIMR = I915_READ(IMR);
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}
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}
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if (IS_GEN4(dev))
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pci_read_config_word(dev->pdev, GCDGMBUS,
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&dev_priv->regfile.saveGCDGMBUS);
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/* Cache mode state */
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if (INTEL_INFO(dev)->gen < 7)
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dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
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/* Memory Arbitration state */
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dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
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/* Scratch space */
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for (i = 0; i < 16; i++) {
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dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
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dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
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}
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for (i = 0; i < 3; i++)
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dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
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mutex_unlock(&dev->struct_mutex);
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return 0;
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}
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int i915_restore_state(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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mutex_lock(&dev->struct_mutex);
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i915_gem_restore_fences(dev);
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if (IS_GEN4(dev))
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pci_write_config_word(dev->pdev, GCDGMBUS,
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dev_priv->regfile.saveGCDGMBUS);
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i915_restore_display(dev);
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if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
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/* Interrupt state */
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if (HAS_PCH_SPLIT(dev)) {
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I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
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I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
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I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
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I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
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I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
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I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
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I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
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I915_WRITE(RSTDBYCTL,
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dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
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} else {
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I915_WRITE(IER, dev_priv->regfile.saveIER);
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I915_WRITE(IMR, dev_priv->regfile.saveIMR);
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}
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}
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/* Cache mode state */
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if (INTEL_INFO(dev)->gen < 7)
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I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
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0xffff0000);
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/* Memory arbitration state */
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I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
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for (i = 0; i < 16; i++) {
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I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
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I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
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}
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for (i = 0; i < 3; i++)
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I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
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mutex_unlock(&dev->struct_mutex);
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intel_i2c_reset(dev);
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return 0;
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}
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