forked from Minki/linux
c8c8d080ed
1. Move the mei_data2slots to mei_dev.h as it will be used by the all supported HW. 2. Change return value from u8 to u32 to catch possible overflows 3. Eliminate computing the slots number twice in the same function Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
578 lines
14 KiB
C
578 lines
14 KiB
C
/*
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*
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* Intel Management Engine Interface (Intel MEI) Linux driver
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* Copyright (c) 2003-2012, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/pci.h>
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#include <linux/kthread.h>
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#include <linux/interrupt.h>
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#include "mei_dev.h"
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#include "hw-me.h"
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#include "hbm.h"
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/**
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* mei_reg_read - Reads 32bit data from the mei device
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*
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* @dev: the device structure
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* @offset: offset from which to read the data
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*
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* returns register value (u32)
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*/
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static inline u32 mei_reg_read(const struct mei_me_hw *hw,
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unsigned long offset)
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{
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return ioread32(hw->mem_addr + offset);
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}
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/**
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* mei_reg_write - Writes 32bit data to the mei device
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*
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* @dev: the device structure
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* @offset: offset from which to write the data
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* @value: register value to write (u32)
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*/
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static inline void mei_reg_write(const struct mei_me_hw *hw,
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unsigned long offset, u32 value)
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{
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iowrite32(value, hw->mem_addr + offset);
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}
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/**
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* mei_mecbrw_read - Reads 32bit data from ME circular buffer
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* read window register
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*
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* @dev: the device structure
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*
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* returns ME_CB_RW register value (u32)
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*/
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static u32 mei_me_mecbrw_read(const struct mei_device *dev)
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{
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return mei_reg_read(to_me_hw(dev), ME_CB_RW);
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}
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/**
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* mei_mecsr_read - Reads 32bit data from the ME CSR
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*
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* @dev: the device structure
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*
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* returns ME_CSR_HA register value (u32)
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*/
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static inline u32 mei_mecsr_read(const struct mei_me_hw *hw)
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{
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return mei_reg_read(hw, ME_CSR_HA);
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}
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/**
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* mei_hcsr_read - Reads 32bit data from the host CSR
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*
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* @dev: the device structure
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*
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* returns H_CSR register value (u32)
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*/
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static inline u32 mei_hcsr_read(const struct mei_me_hw *hw)
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{
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return mei_reg_read(hw, H_CSR);
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}
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/**
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* mei_hcsr_set - writes H_CSR register to the mei device,
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* and ignores the H_IS bit for it is write-one-to-zero.
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*
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* @dev: the device structure
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*/
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static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr)
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{
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hcsr &= ~H_IS;
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mei_reg_write(hw, H_CSR, hcsr);
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}
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/**
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* me_hw_config - configure hw dependent settings
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*
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* @dev: mei device
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*/
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static void mei_me_hw_config(struct mei_device *dev)
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{
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u32 hcsr = mei_hcsr_read(to_me_hw(dev));
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/* Doesn't change in runtime */
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dev->hbuf_depth = (hcsr & H_CBD) >> 24;
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}
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/**
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* mei_clear_interrupts - clear and stop interrupts
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*
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* @dev: the device structure
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*/
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static void mei_me_intr_clear(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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if ((hcsr & H_IS) == H_IS)
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mei_reg_write(hw, H_CSR, hcsr);
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}
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/**
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* mei_me_intr_enable - enables mei device interrupts
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*
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* @dev: the device structure
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*/
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static void mei_me_intr_enable(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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hcsr |= H_IE;
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mei_hcsr_set(hw, hcsr);
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}
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/**
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* mei_disable_interrupts - disables mei device interrupts
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*
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* @dev: the device structure
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*/
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static void mei_me_intr_disable(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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hcsr &= ~H_IE;
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mei_hcsr_set(hw, hcsr);
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}
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/**
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* mei_me_hw_reset - resets fw via mei csr register.
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*
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* @dev: the device structure
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* @interrupts_enabled: if interrupt should be enabled after reset.
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*/
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static void mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(hw);
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dev_dbg(&dev->pdev->dev, "before reset HCSR = 0x%08x.\n", hcsr);
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hcsr |= (H_RST | H_IG);
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if (intr_enable)
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hcsr |= H_IE;
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else
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hcsr &= ~H_IE;
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mei_hcsr_set(hw, hcsr);
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hcsr = mei_hcsr_read(hw) | H_IG;
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hcsr &= ~H_RST;
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mei_hcsr_set(hw, hcsr);
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hcsr = mei_hcsr_read(hw);
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dev_dbg(&dev->pdev->dev, "current HCSR = 0x%08x.\n", hcsr);
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}
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/**
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* mei_me_host_set_ready - enable device
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*
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* @dev - mei device
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* returns bool
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*/
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static void mei_me_host_set_ready(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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hw->host_hw_state |= H_IE | H_IG | H_RDY;
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mei_hcsr_set(hw, hw->host_hw_state);
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}
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/**
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* mei_me_host_is_ready - check whether the host has turned ready
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*
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* @dev - mei device
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* returns bool
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*/
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static bool mei_me_host_is_ready(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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hw->host_hw_state = mei_hcsr_read(hw);
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return (hw->host_hw_state & H_RDY) == H_RDY;
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}
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/**
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* mei_me_hw_is_ready - check whether the me(hw) has turned ready
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*
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* @dev - mei device
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* returns bool
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*/
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static bool mei_me_hw_is_ready(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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hw->me_hw_state = mei_mecsr_read(hw);
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return (hw->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA;
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}
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/**
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* mei_hbuf_filled_slots - gets number of device filled buffer slots
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*
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* @dev: the device structure
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*
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* returns number of filled slots
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*/
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static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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char read_ptr, write_ptr;
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hw->host_hw_state = mei_hcsr_read(hw);
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read_ptr = (char) ((hw->host_hw_state & H_CBRP) >> 8);
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write_ptr = (char) ((hw->host_hw_state & H_CBWP) >> 16);
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return (unsigned char) (write_ptr - read_ptr);
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}
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/**
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* mei_hbuf_is_empty - checks if host buffer is empty.
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*
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* @dev: the device structure
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*
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* returns true if empty, false - otherwise.
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*/
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static bool mei_me_hbuf_is_empty(struct mei_device *dev)
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{
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return mei_hbuf_filled_slots(dev) == 0;
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}
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/**
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* mei_me_hbuf_empty_slots - counts write empty slots.
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*
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* @dev: the device structure
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*
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* returns -1(ESLOTS_OVERFLOW) if overflow, otherwise empty slots count
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*/
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static int mei_me_hbuf_empty_slots(struct mei_device *dev)
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{
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unsigned char filled_slots, empty_slots;
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filled_slots = mei_hbuf_filled_slots(dev);
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empty_slots = dev->hbuf_depth - filled_slots;
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/* check for overflow */
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if (filled_slots > dev->hbuf_depth)
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return -EOVERFLOW;
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return empty_slots;
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}
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static size_t mei_me_hbuf_max_len(const struct mei_device *dev)
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{
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return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr);
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}
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/**
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* mei_write_message - writes a message to mei device.
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*
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* @dev: the device structure
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* @header: mei HECI header of message
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* @buf: message payload will be written
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*
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* This function returns -EIO if write has failed
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*/
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static int mei_me_write_message(struct mei_device *dev,
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struct mei_msg_hdr *header,
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unsigned char *buf)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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unsigned long rem;
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unsigned long length = header->length;
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u32 *reg_buf = (u32 *)buf;
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u32 hcsr;
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u32 dw_cnt;
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int i;
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int empty_slots;
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dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
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empty_slots = mei_hbuf_empty_slots(dev);
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dev_dbg(&dev->pdev->dev, "empty slots = %hu.\n", empty_slots);
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dw_cnt = mei_data2slots(length);
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if (empty_slots < 0 || dw_cnt > empty_slots)
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return -EIO;
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mei_reg_write(hw, H_CB_WW, *((u32 *) header));
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for (i = 0; i < length / 4; i++)
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mei_reg_write(hw, H_CB_WW, reg_buf[i]);
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rem = length & 0x3;
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if (rem > 0) {
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u32 reg = 0;
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memcpy(®, &buf[length - rem], rem);
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mei_reg_write(hw, H_CB_WW, reg);
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}
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hcsr = mei_hcsr_read(hw) | H_IG;
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mei_hcsr_set(hw, hcsr);
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if (!mei_me_hw_is_ready(dev))
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return -EIO;
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return 0;
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}
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/**
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* mei_me_count_full_read_slots - counts read full slots.
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*
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* @dev: the device structure
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*
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* returns -1(ESLOTS_OVERFLOW) if overflow, otherwise filled slots count
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*/
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static int mei_me_count_full_read_slots(struct mei_device *dev)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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char read_ptr, write_ptr;
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unsigned char buffer_depth, filled_slots;
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hw->me_hw_state = mei_mecsr_read(hw);
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buffer_depth = (unsigned char)((hw->me_hw_state & ME_CBD_HRA) >> 24);
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read_ptr = (char) ((hw->me_hw_state & ME_CBRP_HRA) >> 8);
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write_ptr = (char) ((hw->me_hw_state & ME_CBWP_HRA) >> 16);
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filled_slots = (unsigned char) (write_ptr - read_ptr);
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/* check for overflow */
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if (filled_slots > buffer_depth)
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return -EOVERFLOW;
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dev_dbg(&dev->pdev->dev, "filled_slots =%08x\n", filled_slots);
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return (int)filled_slots;
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}
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/**
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* mei_me_read_slots - reads a message from mei device.
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*
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* @dev: the device structure
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* @buffer: message buffer will be written
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* @buffer_length: message size will be read
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*/
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static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
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unsigned long buffer_length)
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{
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 *reg_buf = (u32 *)buffer;
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u32 hcsr;
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for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
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*reg_buf++ = mei_me_mecbrw_read(dev);
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if (buffer_length > 0) {
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u32 reg = mei_me_mecbrw_read(dev);
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memcpy(reg_buf, ®, buffer_length);
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}
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hcsr = mei_hcsr_read(hw) | H_IG;
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mei_hcsr_set(hw, hcsr);
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return 0;
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}
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/**
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* mei_me_irq_quick_handler - The ISR of the MEI device
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*
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* @irq: The irq number
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* @dev_id: pointer to the device structure
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*
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* returns irqreturn_t
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*/
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irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
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{
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struct mei_device *dev = (struct mei_device *) dev_id;
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 csr_reg = mei_hcsr_read(hw);
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if ((csr_reg & H_IS) != H_IS)
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return IRQ_NONE;
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/* clear H_IS bit in H_CSR */
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mei_reg_write(hw, H_CSR, csr_reg);
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return IRQ_WAKE_THREAD;
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}
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/**
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* mei_me_irq_thread_handler - function called after ISR to handle the interrupt
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* processing.
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*
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* @irq: The irq number
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* @dev_id: pointer to the device structure
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*
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* returns irqreturn_t
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*
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*/
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irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
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{
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struct mei_device *dev = (struct mei_device *) dev_id;
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struct mei_cl_cb complete_list;
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struct mei_cl_cb *cb_pos = NULL, *cb_next = NULL;
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struct mei_cl *cl;
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s32 slots;
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int rets;
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bool bus_message_received;
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dev_dbg(&dev->pdev->dev, "function called after ISR to handle the interrupt processing.\n");
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/* initialize our complete list */
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mutex_lock(&dev->device_lock);
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mei_io_list_init(&complete_list);
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/* Ack the interrupt here
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* In case of MSI we don't go through the quick handler */
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if (pci_dev_msi_enabled(dev->pdev))
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mei_clear_interrupts(dev);
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/* check if ME wants a reset */
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if (!mei_hw_is_ready(dev) &&
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dev->dev_state != MEI_DEV_RESETING &&
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dev->dev_state != MEI_DEV_INITIALIZING) {
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dev_dbg(&dev->pdev->dev, "FW not ready.\n");
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mei_reset(dev, 1);
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mutex_unlock(&dev->device_lock);
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return IRQ_HANDLED;
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}
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/* check if we need to start the dev */
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if (!mei_host_is_ready(dev)) {
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if (mei_hw_is_ready(dev)) {
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dev_dbg(&dev->pdev->dev, "we need to start the dev.\n");
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mei_host_set_ready(dev);
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dev_dbg(&dev->pdev->dev, "link is established start sending messages.\n");
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/* link is established * start sending messages. */
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dev->dev_state = MEI_DEV_INIT_CLIENTS;
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mei_hbm_start_req(dev);
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mutex_unlock(&dev->device_lock);
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return IRQ_HANDLED;
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} else {
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dev_dbg(&dev->pdev->dev, "FW not ready.\n");
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mutex_unlock(&dev->device_lock);
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return IRQ_HANDLED;
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}
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}
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/* check slots available for reading */
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slots = mei_count_full_read_slots(dev);
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while (slots > 0) {
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/* we have urgent data to send so break the read */
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if (dev->wr_ext_msg.hdr.length)
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break;
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dev_dbg(&dev->pdev->dev, "slots =%08x\n", slots);
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dev_dbg(&dev->pdev->dev, "call mei_irq_read_handler.\n");
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rets = mei_irq_read_handler(dev, &complete_list, &slots);
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if (rets)
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goto end;
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}
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rets = mei_irq_write_handler(dev, &complete_list);
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end:
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dev_dbg(&dev->pdev->dev, "end of bottom half function.\n");
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dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
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bus_message_received = false;
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if (dev->recvd_msg && waitqueue_active(&dev->wait_recvd_msg)) {
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dev_dbg(&dev->pdev->dev, "received waiting bus message\n");
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bus_message_received = true;
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}
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mutex_unlock(&dev->device_lock);
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if (bus_message_received) {
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dev_dbg(&dev->pdev->dev, "wake up dev->wait_recvd_msg\n");
|
|
wake_up_interruptible(&dev->wait_recvd_msg);
|
|
bus_message_received = false;
|
|
}
|
|
if (list_empty(&complete_list.list))
|
|
return IRQ_HANDLED;
|
|
|
|
|
|
list_for_each_entry_safe(cb_pos, cb_next, &complete_list.list, list) {
|
|
cl = cb_pos->cl;
|
|
list_del(&cb_pos->list);
|
|
if (cl) {
|
|
if (cl != &dev->iamthif_cl) {
|
|
dev_dbg(&dev->pdev->dev, "completing call back.\n");
|
|
mei_irq_complete_handler(cl, cb_pos);
|
|
cb_pos = NULL;
|
|
} else if (cl == &dev->iamthif_cl) {
|
|
mei_amthif_complete(dev, cb_pos);
|
|
}
|
|
}
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
static const struct mei_hw_ops mei_me_hw_ops = {
|
|
|
|
.host_set_ready = mei_me_host_set_ready,
|
|
.host_is_ready = mei_me_host_is_ready,
|
|
|
|
.hw_is_ready = mei_me_hw_is_ready,
|
|
.hw_reset = mei_me_hw_reset,
|
|
.hw_config = mei_me_hw_config,
|
|
|
|
.intr_clear = mei_me_intr_clear,
|
|
.intr_enable = mei_me_intr_enable,
|
|
.intr_disable = mei_me_intr_disable,
|
|
|
|
.hbuf_free_slots = mei_me_hbuf_empty_slots,
|
|
.hbuf_is_ready = mei_me_hbuf_is_empty,
|
|
.hbuf_max_len = mei_me_hbuf_max_len,
|
|
|
|
.write = mei_me_write_message,
|
|
|
|
.rdbuf_full_slots = mei_me_count_full_read_slots,
|
|
.read_hdr = mei_me_mecbrw_read,
|
|
.read = mei_me_read_slots
|
|
};
|
|
|
|
/**
|
|
* init_mei_device - allocates and initializes the mei device structure
|
|
*
|
|
* @pdev: The pci device structure
|
|
*
|
|
* returns The mei_device_device pointer on success, NULL on failure.
|
|
*/
|
|
struct mei_device *mei_me_dev_init(struct pci_dev *pdev)
|
|
{
|
|
struct mei_device *dev;
|
|
|
|
dev = kzalloc(sizeof(struct mei_device) +
|
|
sizeof(struct mei_me_hw), GFP_KERNEL);
|
|
if (!dev)
|
|
return NULL;
|
|
|
|
mei_device_init(dev);
|
|
|
|
INIT_LIST_HEAD(&dev->wd_cl.link);
|
|
INIT_LIST_HEAD(&dev->iamthif_cl.link);
|
|
mei_io_list_init(&dev->amthif_cmd_list);
|
|
mei_io_list_init(&dev->amthif_rd_complete_list);
|
|
|
|
INIT_DELAYED_WORK(&dev->timer_work, mei_timer);
|
|
INIT_WORK(&dev->init_work, mei_host_client_init);
|
|
|
|
dev->ops = &mei_me_hw_ops;
|
|
|
|
dev->pdev = pdev;
|
|
return dev;
|
|
}
|
|
|