1deab8ce2c
Pull sparc updates from David Miller:
1) Add missing cmpxchg64() for 32-bit sparc.
2) Timer conversions from Allen Pais and Kees Cook.
3) vDSO support, from Nagarathnam Muthusamy.
4) Fix sparc64 huge page table walks based upon bug report by Al Viro,
from Nitin Gupta.
5) Optimized fls() for T4 and above, from Vijay Kumar.
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc:
sparc64: Fix page table walk for PUD hugepages
sparc64: Convert timers to user timer_setup()
sparc64: convert mdesc_handle.refcnt from atomic_t to refcount_t
sparc/led: Convert timers to use timer_setup()
sparc64: Use sparc optimized fls and __fls for T4 and above
sparc64: SPARC optimized __fls function
sparc64: SPARC optimized fls function
sparc64: Define SPARC default __fls function
sparc64: Define SPARC default fls function
vDSO for sparc
sparc32: Add cmpxchg64().
sbus: char: Move D7S_MINOR to include/linux/miscdevice.h
sparc: time: Remove unneeded linux/miscdevice.h include
sparc64: mmu_context: Add missing include files
113 lines
3.1 KiB
C
113 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __MMU_H
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#define __MMU_H
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#include <linux/const.h>
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#include <asm/page.h>
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#include <asm/hypervisor.h>
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#define CTX_NR_BITS 13
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#define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))
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/* UltraSPARC-III+ and later have a feature whereby you can
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* select what page size the various Data-TLB instances in the
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* chip. In order to gracefully support this, we put the version
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* field in a spot outside of the areas of the context register
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* where this parameter is specified.
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*/
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#define CTX_VERSION_SHIFT 22
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#define CTX_VERSION_MASK ((~0UL) << CTX_VERSION_SHIFT)
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#define CTX_PGSZ_8KB _AC(0x0,UL)
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#define CTX_PGSZ_64KB _AC(0x1,UL)
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#define CTX_PGSZ_512KB _AC(0x2,UL)
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#define CTX_PGSZ_4MB _AC(0x3,UL)
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#define CTX_PGSZ_BITS _AC(0x7,UL)
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#define CTX_PGSZ0_NUC_SHIFT 61
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#define CTX_PGSZ1_NUC_SHIFT 58
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#define CTX_PGSZ0_SHIFT 16
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#define CTX_PGSZ1_SHIFT 19
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#define CTX_PGSZ_MASK ((CTX_PGSZ_BITS << CTX_PGSZ0_SHIFT) | \
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(CTX_PGSZ_BITS << CTX_PGSZ1_SHIFT))
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#define CTX_PGSZ_BASE CTX_PGSZ_8KB
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#define CTX_PGSZ_HUGE CTX_PGSZ_4MB
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#define CTX_PGSZ_KERN CTX_PGSZ_4MB
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/* Thus, when running on UltraSPARC-III+ and later, we use the following
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* PRIMARY_CONTEXT register values for the kernel context.
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*/
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#define CTX_CHEETAH_PLUS_NUC \
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((CTX_PGSZ_KERN << CTX_PGSZ0_NUC_SHIFT) | \
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(CTX_PGSZ_BASE << CTX_PGSZ1_NUC_SHIFT))
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#define CTX_CHEETAH_PLUS_CTX0 \
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((CTX_PGSZ_KERN << CTX_PGSZ0_SHIFT) | \
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(CTX_PGSZ_BASE << CTX_PGSZ1_SHIFT))
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/* If you want "the TLB context number" use CTX_NR_MASK. If you
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* want "the bits I program into the context registers" use
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* CTX_HW_MASK.
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*/
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#define CTX_NR_MASK TAG_CONTEXT_BITS
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#define CTX_HW_MASK (CTX_NR_MASK | CTX_PGSZ_MASK)
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#define CTX_FIRST_VERSION BIT(CTX_VERSION_SHIFT)
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#define CTX_VALID(__ctx) \
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(!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK))
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#define CTX_HWBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_HW_MASK)
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#define CTX_NRBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_NR_MASK)
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#ifndef __ASSEMBLY__
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#define TSB_ENTRY_ALIGNMENT 16
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struct tsb {
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unsigned long tag;
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unsigned long pte;
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} __attribute__((aligned(TSB_ENTRY_ALIGNMENT)));
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void __tsb_insert(unsigned long ent, unsigned long tag, unsigned long pte);
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void tsb_flush(unsigned long ent, unsigned long tag);
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void tsb_init(struct tsb *tsb, unsigned long size);
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struct tsb_config {
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struct tsb *tsb;
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unsigned long tsb_rss_limit;
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unsigned long tsb_nentries;
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unsigned long tsb_reg_val;
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unsigned long tsb_map_vaddr;
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unsigned long tsb_map_pte;
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};
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#define MM_TSB_BASE 0
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#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
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#define MM_TSB_HUGE 1
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#define MM_NUM_TSBS 2
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#else
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#define MM_NUM_TSBS 1
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#endif
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typedef struct {
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spinlock_t lock;
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unsigned long sparc64_ctx_val;
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unsigned long hugetlb_pte_count;
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unsigned long thp_pte_count;
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struct tsb_config tsb_block[MM_NUM_TSBS];
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struct hv_tsb_descr tsb_descr[MM_NUM_TSBS];
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void *vdso;
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} mm_context_t;
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#endif /* !__ASSEMBLY__ */
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#define TSB_CONFIG_TSB 0x00
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#define TSB_CONFIG_RSS_LIMIT 0x08
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#define TSB_CONFIG_NENTRIES 0x10
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#define TSB_CONFIG_REG_VAL 0x18
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#define TSB_CONFIG_MAP_VADDR 0x20
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#define TSB_CONFIG_MAP_PTE 0x28
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#endif /* __MMU_H */
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