d74361881f
This adds a new XICS backend that uses OPAL calls, which can be used when we don't have native support for the platform interrupt controller. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
145 lines
3.0 KiB
C
145 lines
3.0 KiB
C
/*
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* Copyright 2016 IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/cpu.h>
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#include <linux/of.h>
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#include <asm/smp.h>
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#include <asm/irq.h>
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#include <asm/errno.h>
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#include <asm/xics.h>
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#include <asm/io.h>
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#include <asm/opal.h>
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static void icp_opal_teardown_cpu(void)
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{
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int cpu = smp_processor_id();
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/* Clear any pending IPI */
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opal_int_set_mfrr(cpu, 0xff);
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}
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static void icp_opal_flush_ipi(void)
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{
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/*
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* We take the ipi irq but and never return so we need to EOI the IPI,
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* but want to leave our priority 0.
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*
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* Should we check all the other interrupts too?
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* Should we be flagging idle loop instead?
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* Or creating some task to be scheduled?
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*/
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opal_int_eoi((0x00 << 24) | XICS_IPI);
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}
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static unsigned int icp_opal_get_irq(void)
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{
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unsigned int xirr;
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unsigned int vec;
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unsigned int irq;
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int64_t rc;
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rc = opal_int_get_xirr(&xirr, false);
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if (rc < 0)
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return NO_IRQ;
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xirr = be32_to_cpu(xirr);
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vec = xirr & 0x00ffffff;
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if (vec == XICS_IRQ_SPURIOUS)
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return NO_IRQ;
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irq = irq_find_mapping(xics_host, vec);
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if (likely(irq != NO_IRQ)) {
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xics_push_cppr(vec);
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return irq;
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}
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/* We don't have a linux mapping, so have rtas mask it. */
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xics_mask_unknown_vec(vec);
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/* We might learn about it later, so EOI it */
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opal_int_eoi(xirr);
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return NO_IRQ;
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}
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static void icp_opal_set_cpu_priority(unsigned char cppr)
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{
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xics_set_base_cppr(cppr);
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opal_int_set_cppr(cppr);
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iosync();
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}
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static void icp_opal_eoi(struct irq_data *d)
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{
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unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
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int64_t rc;
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iosync();
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rc = opal_int_eoi((xics_pop_cppr() << 24) | hw_irq);
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/*
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* EOI tells us whether there are more interrupts to fetch.
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*
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* Some HW implementations might not be able to send us another
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* external interrupt in that case, so we force a replay.
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*/
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if (rc > 0)
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force_external_irq_replay();
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}
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#ifdef CONFIG_SMP
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static void icp_opal_cause_ipi(int cpu, unsigned long data)
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{
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opal_int_set_mfrr(cpu, IPI_PRIORITY);
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}
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static irqreturn_t icp_opal_ipi_action(int irq, void *dev_id)
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{
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int cpu = smp_processor_id();
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opal_int_set_mfrr(cpu, 0xff);
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return smp_ipi_demux();
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}
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#endif /* CONFIG_SMP */
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static const struct icp_ops icp_opal_ops = {
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.get_irq = icp_opal_get_irq,
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.eoi = icp_opal_eoi,
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.set_priority = icp_opal_set_cpu_priority,
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.teardown_cpu = icp_opal_teardown_cpu,
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.flush_ipi = icp_opal_flush_ipi,
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#ifdef CONFIG_SMP
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.ipi_action = icp_opal_ipi_action,
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.cause_ipi = icp_opal_cause_ipi,
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#endif
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};
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int icp_opal_init(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "ibm,opal-intc");
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if (!np)
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return -ENODEV;
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icp_ops = &icp_opal_ops;
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printk("XICS: Using OPAL ICP fallbacks\n");
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return 0;
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}
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