linux/drivers/gpu
Nicholas Kazlauskas c856f16c33 drm/amd/display: Set optimize_pwr_state for DCN31
[Why]
We'll exit optimized power state to do link detection but we won't enter
back into the optimized power state.

This could potentially block s2idle entry depending on the sequencing,
but it also means we're losing some power during the transition period.

[How]
Hook up the handler like DCN21. It was also missed like the
exit_optimized_pwr_state callback.

Fixes: 64b1d0e8d5 ("drm/amd/display: Add DCN3.1 HWSEQ")

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Eric Yang <Eric.Yang2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-30 08:54:44 -05:00
..
drm drm/amd/display: Set optimize_pwr_state for DCN31 2021-12-30 08:54:44 -05:00
host1x gpu: host1x: Plug potential memory leak 2021-09-16 18:06:52 +02:00
ipu-v3 media: i.MX6: Support 16-bit BT.1120 video input 2021-10-19 08:08:38 +01:00
trace
vga
Makefile