forked from Minki/linux
73c154c60b
For the hypervisor to take advantage of the MWAIT support it needs to extract from the ACPI _CST the register address. But the hypervisor does not have the support to parse DSDT so it relies on the initial domain (dom0) to parse the ACPI Power Management information and push it up to the hypervisor. The pushing of the data is done by the processor_harveset_xen module which parses the information that the ACPI parser has graciously exposed in 'struct acpi_processor'. For the ACPI parser to also expose the Cx states for MWAIT, we need to expose the MWAIT capability (leaf 1). Furthermore we also need to expose the MWAIT_LEAF capability (leaf 5) for cstate.c to properly function. The hypervisor could expose these flags when it traps the XEN_EMULATE_PREFIX operations, but it can't do it since it needs to be backwards compatible. Instead we choose to use the native CPUID to figure out if the MWAIT capability exists and use the XEN_SET_PDC query hypercall to figure out if the hypervisor wants us to expose the MWAIT_LEAF capability or not. Note: The XEN_SET_PDC query was implemented in c/s 23783: "ACPI: add _PDC input override mechanism". With this in place, instead of C3 ACPI IOPORT 415 we get now C3:ACPI FFH INTEL MWAIT 0x20 Note: The cpu_idle which would be calling the mwait variants for idling never gets set b/c we set the default pm_idle to be the hypercall variant. Acked-by: Jan Beulich <JBeulich@suse.com> [v2: Fix missing header file include and #ifdef] Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
178 lines
6.0 KiB
C
178 lines
6.0 KiB
C
/******************************************************************************
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* arch-x86_32.h
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*
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* Guest OS interface to x86 Xen.
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*
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* Copyright (c) 2004, K A Fraser
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*/
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#ifndef _ASM_X86_XEN_INTERFACE_H
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#define _ASM_X86_XEN_INTERFACE_H
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#ifdef __XEN__
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#define __DEFINE_GUEST_HANDLE(name, type) \
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typedef struct { type *p; } __guest_handle_ ## name
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#else
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#define __DEFINE_GUEST_HANDLE(name, type) \
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typedef type * __guest_handle_ ## name
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#endif
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#define DEFINE_GUEST_HANDLE_STRUCT(name) \
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__DEFINE_GUEST_HANDLE(name, struct name)
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#define DEFINE_GUEST_HANDLE(name) __DEFINE_GUEST_HANDLE(name, name)
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#define GUEST_HANDLE(name) __guest_handle_ ## name
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#ifdef __XEN__
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#if defined(__i386__)
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#define set_xen_guest_handle(hnd, val) \
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do { \
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if (sizeof(hnd) == 8) \
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*(uint64_t *)&(hnd) = 0; \
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(hnd).p = val; \
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} while (0)
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#elif defined(__x86_64__)
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#define set_xen_guest_handle(hnd, val) do { (hnd).p = val; } while (0)
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#endif
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#else
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#if defined(__i386__)
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#define set_xen_guest_handle(hnd, val) \
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do { \
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if (sizeof(hnd) == 8) \
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*(uint64_t *)&(hnd) = 0; \
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(hnd) = val; \
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} while (0)
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#elif defined(__x86_64__)
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#define set_xen_guest_handle(hnd, val) do { (hnd) = val; } while (0)
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#endif
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#endif
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#ifndef __ASSEMBLY__
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/* Guest handles for primitive C types. */
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__DEFINE_GUEST_HANDLE(uchar, unsigned char);
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__DEFINE_GUEST_HANDLE(uint, unsigned int);
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__DEFINE_GUEST_HANDLE(ulong, unsigned long);
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DEFINE_GUEST_HANDLE(char);
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DEFINE_GUEST_HANDLE(int);
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DEFINE_GUEST_HANDLE(long);
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DEFINE_GUEST_HANDLE(void);
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DEFINE_GUEST_HANDLE(uint64_t);
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DEFINE_GUEST_HANDLE(uint32_t);
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#endif
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#ifndef HYPERVISOR_VIRT_START
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#define HYPERVISOR_VIRT_START mk_unsigned_long(__HYPERVISOR_VIRT_START)
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#endif
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#define MACH2PHYS_VIRT_START mk_unsigned_long(__MACH2PHYS_VIRT_START)
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#define MACH2PHYS_VIRT_END mk_unsigned_long(__MACH2PHYS_VIRT_END)
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#define MACH2PHYS_NR_ENTRIES ((MACH2PHYS_VIRT_END-MACH2PHYS_VIRT_START)>>__MACH2PHYS_SHIFT)
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/* Maximum number of virtual CPUs in multi-processor guests. */
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#define MAX_VIRT_CPUS 32
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/*
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* SEGMENT DESCRIPTOR TABLES
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*/
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/*
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* A number of GDT entries are reserved by Xen. These are not situated at the
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* start of the GDT because some stupid OSes export hard-coded selector values
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* in their ABI. These hard-coded values are always near the start of the GDT,
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* so Xen places itself out of the way, at the far end of the GDT.
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*/
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#define FIRST_RESERVED_GDT_PAGE 14
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#define FIRST_RESERVED_GDT_BYTE (FIRST_RESERVED_GDT_PAGE * 4096)
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#define FIRST_RESERVED_GDT_ENTRY (FIRST_RESERVED_GDT_BYTE / 8)
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/*
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* Send an array of these to HYPERVISOR_set_trap_table()
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* The privilege level specifies which modes may enter a trap via a software
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* interrupt. On x86/64, since rings 1 and 2 are unavailable, we allocate
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* privilege levels as follows:
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* Level == 0: No one may enter
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* Level == 1: Kernel may enter
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* Level == 2: Kernel may enter
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* Level == 3: Everyone may enter
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*/
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#define TI_GET_DPL(_ti) ((_ti)->flags & 3)
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#define TI_GET_IF(_ti) ((_ti)->flags & 4)
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#define TI_SET_DPL(_ti, _dpl) ((_ti)->flags |= (_dpl))
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#define TI_SET_IF(_ti, _if) ((_ti)->flags |= ((!!(_if))<<2))
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#ifndef __ASSEMBLY__
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struct trap_info {
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uint8_t vector; /* exception vector */
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uint8_t flags; /* 0-3: privilege level; 4: clear event enable? */
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uint16_t cs; /* code selector */
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unsigned long address; /* code offset */
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};
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DEFINE_GUEST_HANDLE_STRUCT(trap_info);
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struct arch_shared_info {
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unsigned long max_pfn; /* max pfn that appears in table */
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/* Frame containing list of mfns containing list of mfns containing p2m. */
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unsigned long pfn_to_mfn_frame_list_list;
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unsigned long nmi_reason;
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};
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#endif /* !__ASSEMBLY__ */
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#ifdef CONFIG_X86_32
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#include "interface_32.h"
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#else
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#include "interface_64.h"
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#endif
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#ifndef __ASSEMBLY__
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/*
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* The following is all CPU context. Note that the fpu_ctxt block is filled
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* in by FXSAVE if the CPU has feature FXSR; otherwise FSAVE is used.
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*/
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struct vcpu_guest_context {
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/* FPU registers come first so they can be aligned for FXSAVE/FXRSTOR. */
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struct { char x[512]; } fpu_ctxt; /* User-level FPU registers */
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#define VGCF_I387_VALID (1<<0)
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#define VGCF_HVM_GUEST (1<<1)
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#define VGCF_IN_KERNEL (1<<2)
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unsigned long flags; /* VGCF_* flags */
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struct cpu_user_regs user_regs; /* User-level CPU registers */
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struct trap_info trap_ctxt[256]; /* Virtual IDT */
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unsigned long ldt_base, ldt_ents; /* LDT (linear address, # ents) */
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unsigned long gdt_frames[16], gdt_ents; /* GDT (machine frames, # ents) */
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unsigned long kernel_ss, kernel_sp; /* Virtual TSS (only SS1/SP1) */
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/* NB. User pagetable on x86/64 is placed in ctrlreg[1]. */
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unsigned long ctrlreg[8]; /* CR0-CR7 (control registers) */
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unsigned long debugreg[8]; /* DB0-DB7 (debug registers) */
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#ifdef __i386__
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unsigned long event_callback_cs; /* CS:EIP of event callback */
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unsigned long event_callback_eip;
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unsigned long failsafe_callback_cs; /* CS:EIP of failsafe callback */
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unsigned long failsafe_callback_eip;
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#else
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unsigned long event_callback_eip;
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unsigned long failsafe_callback_eip;
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unsigned long syscall_callback_eip;
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#endif
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unsigned long vm_assist; /* VMASST_TYPE_* bitmap */
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#ifdef __x86_64__
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/* Segment base addresses. */
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uint64_t fs_base;
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uint64_t gs_base_kernel;
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uint64_t gs_base_user;
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#endif
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};
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DEFINE_GUEST_HANDLE_STRUCT(vcpu_guest_context);
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#endif /* !__ASSEMBLY__ */
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/*
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* Prefix forces emulation of some non-trapping instructions.
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* Currently only CPUID.
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*/
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#ifdef __ASSEMBLY__
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#define XEN_EMULATE_PREFIX .byte 0x0f,0x0b,0x78,0x65,0x6e ;
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#define XEN_CPUID XEN_EMULATE_PREFIX cpuid
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#else
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#define XEN_EMULATE_PREFIX ".byte 0x0f,0x0b,0x78,0x65,0x6e ; "
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#define XEN_CPUID XEN_EMULATE_PREFIX "cpuid"
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#endif
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#endif /* _ASM_X86_XEN_INTERFACE_H */
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