c814a2d2d4
Sets default values for each queue cycle start and cycle end. This allows some simplification in the handling of these configurations as most TSN features in i225 require a cycle to be configured. In i225, cycle start and end time is required to be programmed for CBS to work properly. Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com> Signed-off-by: Aravindhan Gunasekaran <aravindhan.gunasekaran@intel.com> Signed-off-by: Mallikarjuna Chilakala <mallikarjuna.chilakala@intel.com> Tested-by: Dvora Fuxbrumer <dvorax.fuxbrumer@linux.intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
152 lines
3.3 KiB
C
152 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2019 Intel Corporation */
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#include "igc.h"
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#include "igc_tsn.h"
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static bool is_any_launchtime(struct igc_adapter *adapter)
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{
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int i;
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for (i = 0; i < adapter->num_tx_queues; i++) {
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struct igc_ring *ring = adapter->tx_ring[i];
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if (ring->launchtime_enable)
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return true;
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}
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return false;
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}
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/* Returns the TSN specific registers to their default values after
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* TSN offloading is disabled.
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*/
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static int igc_tsn_disable_offload(struct igc_adapter *adapter)
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{
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struct igc_hw *hw = &adapter->hw;
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u32 tqavctrl;
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int i;
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if (!(adapter->flags & IGC_FLAG_TSN_QBV_ENABLED))
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return 0;
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adapter->cycle_time = 0;
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wr32(IGC_TXPBS, I225_TXPBSIZE_DEFAULT);
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wr32(IGC_DTXMXPKTSZ, IGC_DTXMXPKTSZ_DEFAULT);
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tqavctrl = rd32(IGC_TQAVCTRL);
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tqavctrl &= ~(IGC_TQAVCTRL_TRANSMIT_MODE_TSN |
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IGC_TQAVCTRL_ENHANCED_QAV);
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wr32(IGC_TQAVCTRL, tqavctrl);
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for (i = 0; i < adapter->num_tx_queues; i++) {
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wr32(IGC_TXQCTL(i), 0);
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wr32(IGC_STQT(i), 0);
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wr32(IGC_ENDQT(i), NSEC_PER_SEC);
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}
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wr32(IGC_QBVCYCLET_S, 0);
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wr32(IGC_QBVCYCLET, NSEC_PER_SEC);
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adapter->flags &= ~IGC_FLAG_TSN_QBV_ENABLED;
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return 0;
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}
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static int igc_tsn_enable_offload(struct igc_adapter *adapter)
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{
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struct igc_hw *hw = &adapter->hw;
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u32 tqavctrl, baset_l, baset_h;
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u32 sec, nsec, cycle;
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ktime_t base_time, systim;
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int i;
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if (adapter->flags & IGC_FLAG_TSN_QBV_ENABLED)
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return 0;
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cycle = adapter->cycle_time;
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base_time = adapter->base_time;
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wr32(IGC_TSAUXC, 0);
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wr32(IGC_DTXMXPKTSZ, IGC_DTXMXPKTSZ_TSN);
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wr32(IGC_TXPBS, IGC_TXPBSIZE_TSN);
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tqavctrl = rd32(IGC_TQAVCTRL);
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tqavctrl |= IGC_TQAVCTRL_TRANSMIT_MODE_TSN | IGC_TQAVCTRL_ENHANCED_QAV;
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wr32(IGC_TQAVCTRL, tqavctrl);
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wr32(IGC_QBVCYCLET_S, cycle);
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wr32(IGC_QBVCYCLET, cycle);
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for (i = 0; i < adapter->num_tx_queues; i++) {
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struct igc_ring *ring = adapter->tx_ring[i];
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u32 txqctl = 0;
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wr32(IGC_STQT(i), ring->start_time);
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wr32(IGC_ENDQT(i), ring->end_time);
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if (adapter->base_time) {
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/* If we have a base_time we are in "taprio"
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* mode and we need to be strict about the
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* cycles: only transmit a packet if it can be
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* completed during that cycle.
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*/
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txqctl |= IGC_TXQCTL_STRICT_CYCLE |
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IGC_TXQCTL_STRICT_END;
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}
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if (ring->launchtime_enable)
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txqctl |= IGC_TXQCTL_QUEUE_MODE_LAUNCHT;
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wr32(IGC_TXQCTL(i), txqctl);
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}
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nsec = rd32(IGC_SYSTIML);
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sec = rd32(IGC_SYSTIMH);
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systim = ktime_set(sec, nsec);
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if (ktime_compare(systim, base_time) > 0) {
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s64 n;
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n = div64_s64(ktime_sub_ns(systim, base_time), cycle);
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base_time = ktime_add_ns(base_time, (n + 1) * cycle);
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}
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baset_h = div_s64_rem(base_time, NSEC_PER_SEC, &baset_l);
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wr32(IGC_BASET_H, baset_h);
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wr32(IGC_BASET_L, baset_l);
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adapter->flags |= IGC_FLAG_TSN_QBV_ENABLED;
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return 0;
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}
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int igc_tsn_offload_apply(struct igc_adapter *adapter)
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{
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bool is_any_enabled = adapter->base_time || is_any_launchtime(adapter);
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if (!(adapter->flags & IGC_FLAG_TSN_QBV_ENABLED) && !is_any_enabled)
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return 0;
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if (!is_any_enabled) {
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int err = igc_tsn_disable_offload(adapter);
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if (err < 0)
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return err;
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/* The BASET registers aren't cleared when writing
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* into them, force a reset if the interface is
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* running.
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*/
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if (netif_running(adapter->netdev))
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schedule_work(&adapter->reset_task);
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return 0;
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}
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return igc_tsn_enable_offload(adapter);
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}
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