58ef3aeb9a
Support newer VIC firmware by accepting the new magic number 0x10fe, loading the full code segment instead of just the first page at boot time, and skipping FCE setup if the firmware header indicates that FCE is handled internally by the firmware. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
224 lines
5.6 KiB
C
224 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015, NVIDIA Corporation.
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*/
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/firmware.h>
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#include <linux/pci_ids.h>
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#include <linux/iopoll.h>
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#include "falcon.h"
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#include "drm.h"
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enum falcon_memory {
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FALCON_MEMORY_IMEM,
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FALCON_MEMORY_DATA,
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};
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static void falcon_writel(struct falcon *falcon, u32 value, u32 offset)
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{
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writel(value, falcon->regs + offset);
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}
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int falcon_wait_idle(struct falcon *falcon)
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{
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u32 value;
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return readl_poll_timeout(falcon->regs + FALCON_IDLESTATE, value,
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(value == 0), 10, 100000);
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}
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static int falcon_dma_wait_idle(struct falcon *falcon)
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{
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u32 value;
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return readl_poll_timeout(falcon->regs + FALCON_DMATRFCMD, value,
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(value & FALCON_DMATRFCMD_IDLE), 10, 100000);
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}
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static int falcon_copy_chunk(struct falcon *falcon,
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phys_addr_t base,
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unsigned long offset,
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enum falcon_memory target)
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{
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u32 cmd = FALCON_DMATRFCMD_SIZE_256B;
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if (target == FALCON_MEMORY_IMEM)
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cmd |= FALCON_DMATRFCMD_IMEM;
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falcon_writel(falcon, offset, FALCON_DMATRFMOFFS);
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falcon_writel(falcon, base, FALCON_DMATRFFBOFFS);
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falcon_writel(falcon, cmd, FALCON_DMATRFCMD);
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return falcon_dma_wait_idle(falcon);
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}
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static void falcon_copy_firmware_image(struct falcon *falcon,
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const struct firmware *firmware)
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{
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u32 *virt = falcon->firmware.virt;
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size_t i;
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/* copy the whole thing taking into account endianness */
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for (i = 0; i < firmware->size / sizeof(u32); i++)
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virt[i] = le32_to_cpu(((u32 *)firmware->data)[i]);
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}
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static int falcon_parse_firmware_image(struct falcon *falcon)
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{
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struct falcon_fw_bin_header_v1 *bin = (void *)falcon->firmware.virt;
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struct falcon_fw_os_header_v1 *os;
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/* endian problems would show up right here */
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if (bin->magic != PCI_VENDOR_ID_NVIDIA && bin->magic != 0x10fe) {
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dev_err(falcon->dev, "incorrect firmware magic\n");
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return -EINVAL;
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}
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/* currently only version 1 is supported */
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if (bin->version != 1) {
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dev_err(falcon->dev, "unsupported firmware version\n");
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return -EINVAL;
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}
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/* check that the firmware size is consistent */
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if (bin->size > falcon->firmware.size) {
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dev_err(falcon->dev, "firmware image size inconsistency\n");
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return -EINVAL;
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}
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os = falcon->firmware.virt + bin->os_header_offset;
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falcon->firmware.bin_data.size = bin->os_size;
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falcon->firmware.bin_data.offset = bin->os_data_offset;
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falcon->firmware.code.offset = os->code_offset;
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falcon->firmware.code.size = os->code_size;
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falcon->firmware.data.offset = os->data_offset;
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falcon->firmware.data.size = os->data_size;
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return 0;
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}
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int falcon_read_firmware(struct falcon *falcon, const char *name)
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{
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int err;
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/* request_firmware prints error if it fails */
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err = request_firmware(&falcon->firmware.firmware, name, falcon->dev);
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if (err < 0)
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return err;
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falcon->firmware.size = falcon->firmware.firmware->size;
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return 0;
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}
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int falcon_load_firmware(struct falcon *falcon)
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{
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const struct firmware *firmware = falcon->firmware.firmware;
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int err;
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/* copy firmware image into local area. this also ensures endianness */
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falcon_copy_firmware_image(falcon, firmware);
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/* parse the image data */
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err = falcon_parse_firmware_image(falcon);
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if (err < 0) {
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dev_err(falcon->dev, "failed to parse firmware image\n");
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return err;
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}
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release_firmware(firmware);
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falcon->firmware.firmware = NULL;
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return 0;
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}
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int falcon_init(struct falcon *falcon)
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{
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falcon->firmware.virt = NULL;
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return 0;
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}
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void falcon_exit(struct falcon *falcon)
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{
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if (falcon->firmware.firmware)
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release_firmware(falcon->firmware.firmware);
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}
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int falcon_boot(struct falcon *falcon)
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{
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unsigned long offset;
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u32 value;
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int err;
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if (!falcon->firmware.virt)
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return -EINVAL;
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err = readl_poll_timeout(falcon->regs + FALCON_DMACTL, value,
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(value & (FALCON_DMACTL_IMEM_SCRUBBING |
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FALCON_DMACTL_DMEM_SCRUBBING)) == 0,
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10, 10000);
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if (err < 0)
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return err;
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falcon_writel(falcon, 0, FALCON_DMACTL);
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/* setup the address of the binary data so Falcon can access it later */
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falcon_writel(falcon, (falcon->firmware.iova +
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falcon->firmware.bin_data.offset) >> 8,
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FALCON_DMATRFBASE);
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/* copy the data segment into Falcon internal memory */
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for (offset = 0; offset < falcon->firmware.data.size; offset += 256)
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falcon_copy_chunk(falcon,
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falcon->firmware.data.offset + offset,
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offset, FALCON_MEMORY_DATA);
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/* copy the code segment into Falcon internal memory */
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for (offset = 0; offset < falcon->firmware.code.size; offset += 256)
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falcon_copy_chunk(falcon, falcon->firmware.code.offset + offset,
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offset, FALCON_MEMORY_IMEM);
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/* setup falcon interrupts */
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falcon_writel(falcon, FALCON_IRQMSET_EXT(0xff) |
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FALCON_IRQMSET_SWGEN1 |
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FALCON_IRQMSET_SWGEN0 |
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FALCON_IRQMSET_EXTERR |
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FALCON_IRQMSET_HALT |
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FALCON_IRQMSET_WDTMR,
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FALCON_IRQMSET);
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falcon_writel(falcon, FALCON_IRQDEST_EXT(0xff) |
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FALCON_IRQDEST_SWGEN1 |
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FALCON_IRQDEST_SWGEN0 |
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FALCON_IRQDEST_EXTERR |
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FALCON_IRQDEST_HALT,
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FALCON_IRQDEST);
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/* enable interface */
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falcon_writel(falcon, FALCON_ITFEN_MTHDEN |
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FALCON_ITFEN_CTXEN,
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FALCON_ITFEN);
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/* boot falcon */
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falcon_writel(falcon, 0x00000000, FALCON_BOOTVEC);
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falcon_writel(falcon, FALCON_CPUCTL_STARTCPU, FALCON_CPUCTL);
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err = falcon_wait_idle(falcon);
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if (err < 0) {
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dev_err(falcon->dev, "Falcon boot failed due to timeout\n");
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return err;
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}
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return 0;
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}
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void falcon_execute_method(struct falcon *falcon, u32 method, u32 data)
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{
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falcon_writel(falcon, method >> 2, FALCON_UCLASS_METHOD_OFFSET);
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falcon_writel(falcon, data, FALCON_UCLASS_METHOD_DATA);
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}
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