forked from Minki/linux
26922c5909
For a long time, gcc has warned about odd configurations on s3c64xx: In file included from arch/arm/plat-samsung/pm.c:34:0: arch/arm/mach-s3c64xx/include/mach/pm-core.h:61:0: warning: "s3c_irqwake_eintallow" redefined #define s3c_irqwake_eintallow ((1 << 28) - 1) In file included from arch/arm/plat-samsung/pm.c:33:0: arch/arm/plat-samsung/include/plat/pm.h:49:0: note: this is the location of the previous definition #define s3c_irqwake_eintallow 0 The definitions of s3c_irqwake_intallow and s3c_irqwake_eintallow are a bit consistent between the various platforms. Things have become easier now that it's only s3c24xx and s3c64xx that use them at all, so I've tried to rearrange the definitions to make it more obvious what is going on. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
129 lines
3.5 KiB
C
129 lines
3.5 KiB
C
/* linux/arch/arm/mach-s3c64xx/include/mach/pm-core.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX - PM core support for arch/arm/plat-s3c/pm.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __MACH_S3C64XX_PM_CORE_H
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#define __MACH_S3C64XX_PM_CORE_H __FILE__
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#include <linux/serial_s3c.h>
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#include <linux/delay.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-clock.h>
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#include <mach/map.h>
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static inline void s3c_pm_debug_init_uart(void)
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{
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u32 tmp = __raw_readl(S3C_PCLK_GATE);
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/* As a note, since the S3C64XX UARTs generally have multiple
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* clock sources, we simply enable PCLK at the moment and hope
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* that the resume settings for the UART are suitable for the
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* use with PCLK.
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*/
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tmp |= S3C_CLKCON_PCLK_UART0;
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tmp |= S3C_CLKCON_PCLK_UART1;
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tmp |= S3C_CLKCON_PCLK_UART2;
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tmp |= S3C_CLKCON_PCLK_UART3;
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__raw_writel(tmp, S3C_PCLK_GATE);
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udelay(10);
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}
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static inline void s3c_pm_arch_prepare_irqs(void)
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{
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/* VIC should have already been taken care of */
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/* clear any pending EINT0 interrupts */
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__raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND);
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}
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static inline void s3c_pm_arch_stop_clocks(void)
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{
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}
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static inline void s3c_pm_arch_show_resume_irqs(void)
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{
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}
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/* make these defines, we currently do not have any need to change
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* the IRQ wake controls depending on the CPU we are running on */
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#ifdef CONFIG_PM_SLEEP
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#define s3c_irqwake_eintallow ((1 << 28) - 1)
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#define s3c_irqwake_intallow (~0)
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#else
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#define s3c_irqwake_eintallow 0
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#define s3c_irqwake_intallow 0
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#endif
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static inline void s3c_pm_arch_update_uart(void __iomem *regs,
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struct pm_uart_save *save)
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{
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u32 ucon = __raw_readl(regs + S3C2410_UCON);
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u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
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u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
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u32 new_ucon;
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u32 delta;
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/* S3C64XX UART blocks only support level interrupts, so ensure that
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* when we restore unused UART blocks we force the level interrupt
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* settigs. */
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save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
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/* We have a constraint on changing the clock type of the UART
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* between UCLKx and PCLK, so ensure that when we restore UCON
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* that the CLK field is correctly modified if the bootloader
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* has changed anything.
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*/
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if (ucon_clk != save_clk) {
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new_ucon = save->ucon;
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delta = ucon_clk ^ save_clk;
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/* change from UCLKx => wrong PCLK,
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* either UCLK can be tested for by a bit-test
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* with UCLK0 */
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if (ucon_clk & S3C6400_UCON_UCLK0 &&
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!(save_clk & S3C6400_UCON_UCLK0) &&
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delta & S3C6400_UCON_PCLK2) {
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new_ucon &= ~S3C6400_UCON_UCLK0;
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} else if (delta == S3C6400_UCON_PCLK2) {
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/* as an precaution, don't change from
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* PCLK2 => PCLK or vice-versa */
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new_ucon ^= S3C6400_UCON_PCLK2;
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}
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S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
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ucon, new_ucon, save->ucon);
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save->ucon = new_ucon;
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}
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}
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static inline void s3c_pm_restored_gpios(void)
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{
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/* ensure sleep mode has been cleared from the system */
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__raw_writel(0, S3C64XX_SLPEN);
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}
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static inline void samsung_pm_saved_gpios(void)
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{
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/* turn on the sleep mode and keep it there, as it seems that during
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* suspend the xCON registers get re-set and thus you can end up with
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* problems between going to sleep and resuming.
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*/
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__raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN);
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}
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#endif /* __MACH_S3C64XX_PM_CORE_H */
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