forked from Minki/linux
794d15b25d
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring (depending on the model) one or two Feroceon CPU cores with 512K of L2 cache and VFP coprocessors running at (depending on the model) between 800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe interfaces that can each run either in x4 or quad x1 mode, three USB 2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI interface, four UARTs, and depending on the model, two or four gigabit ethernet interfaces. This patch adds basic support for the platform, and allows booting on the MV78x00 development board, with functional UARTs, SATA, PCIe, GigE and USB ports. Signed-off-by: Stanislav Samsonov <samsonov@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
157 lines
3.6 KiB
C
157 lines
3.6 KiB
C
/*
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* arch/arm/mach-mv78xx0/addr-map.c
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*
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* Address map functions for Marvell MV78xx0 SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mbus.h>
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#include <asm/io.h>
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#include "common.h"
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/*
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* Generic Address Decode Windows bit settings
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*/
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#define TARGET_DDR 0
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#define TARGET_DEV_BUS 1
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#define TARGET_PCIE0 4
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#define TARGET_PCIE1 8
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#define TARGET_PCIE(i) ((i) ? TARGET_PCIE1 : TARGET_PCIE0)
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#define ATTR_DEV_SPI_ROM 0x1f
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#define ATTR_DEV_BOOT 0x2f
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#define ATTR_DEV_CS3 0x37
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#define ATTR_DEV_CS2 0x3b
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#define ATTR_DEV_CS1 0x3d
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#define ATTR_DEV_CS0 0x3e
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#define ATTR_PCIE_IO(l) (0xf0 & ~(0x10 << (l)))
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#define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l)))
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/*
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* Helpers to get DDR bank info
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*/
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#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
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#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
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/*
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* CPU Address Decode Windows registers
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*/
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#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
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#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
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#define WIN_CTRL_OFF 0x0000
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#define WIN_BASE_OFF 0x0004
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#define WIN_REMAP_LO_OFF 0x0008
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#define WIN_REMAP_HI_OFF 0x000c
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struct mbus_dram_target_info mv78xx0_mbus_dram_info;
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static void __init __iomem *win_cfg_base(int win)
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{
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/*
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* Find the control register base address for this window.
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*
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* BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's)
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* MBUS bridge depending on which CPU core we're running on,
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* so we don't need to take that into account here.
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*/
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return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
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}
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static int __init cpu_win_can_remap(int win)
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{
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if (win < 8)
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return 1;
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return 0;
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}
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static void __init setup_cpu_win(int win, u32 base, u32 size,
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u8 target, u8 attr, int remap)
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{
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void __iomem *addr = win_cfg_base(win);
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u32 ctrl;
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base &= 0xffff0000;
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ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
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writel(base, addr + WIN_BASE_OFF);
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writel(ctrl, addr + WIN_CTRL_OFF);
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if (cpu_win_can_remap(win)) {
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if (remap < 0)
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remap = base;
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writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
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writel(0, addr + WIN_REMAP_HI_OFF);
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}
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}
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void __init mv78xx0_setup_cpu_mbus(void)
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{
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void __iomem *addr;
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int i;
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int cs;
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/*
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* First, disable and clear windows.
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*/
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for (i = 0; i < 14; i++) {
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addr = win_cfg_base(i);
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writel(0, addr + WIN_BASE_OFF);
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writel(0, addr + WIN_CTRL_OFF);
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if (cpu_win_can_remap(i)) {
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writel(0, addr + WIN_REMAP_LO_OFF);
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writel(0, addr + WIN_REMAP_HI_OFF);
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}
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}
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/*
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* Setup MBUS dram target info.
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*/
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mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
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if (mv78xx0_core_index() == 0)
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addr = (void __iomem *)DDR_WINDOW_CPU0_BASE;
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else
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addr = (void __iomem *)DDR_WINDOW_CPU1_BASE;
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for (i = 0, cs = 0; i < 4; i++) {
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u32 base = readl(addr + DDR_BASE_CS_OFF(i));
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u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
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/*
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* Chip select enabled?
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*/
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if (size & 1) {
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struct mbus_dram_window *w;
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w = &mv78xx0_mbus_dram_info.cs[cs++];
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w->cs_index = i;
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w->mbus_attr = 0xf & ~(1 << i);
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w->base = base & 0xffff0000;
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w->size = (size | 0x0000ffff) + 1;
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}
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}
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mv78xx0_mbus_dram_info.num_cs = cs;
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}
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void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
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int maj, int min)
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{
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setup_cpu_win(window, base, size, TARGET_PCIE(maj),
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ATTR_PCIE_IO(min), -1);
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}
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void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
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int maj, int min)
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{
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setup_cpu_win(window, base, size, TARGET_PCIE(maj),
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ATTR_PCIE_MEM(min), -1);
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}
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