forked from Minki/linux
dcb36ce9d9
On MMIO relaxed-order platforms, it is possible for the proper delay during NVRAM access to begin before the request passes through the PCI bus (via a MMIO write) to the ISP. Thus, causing a subsequent read to the NVRAM part to fail. Add a MMIO read, after the MMIO write to insure any posted writes are flushed. Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
695 lines
16 KiB
C
695 lines
16 KiB
C
/*
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* QLogic Fibre Channel HBA Driver
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* Copyright (c) 2003-2005 QLogic Corporation
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*
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* See LICENSE.qla2xxx for copyright and licensing details.
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*/
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#include "qla_def.h"
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#include <linux/delay.h>
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#include <asm/uaccess.h>
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static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t);
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static void qla2x00_nv_deselect(scsi_qla_host_t *);
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static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t);
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/*
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* NVRAM support routines
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*/
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/**
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* qla2x00_lock_nvram_access() -
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* @ha: HA context
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*/
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void
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qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
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{
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uint16_t data;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
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data = RD_REG_WORD(®->nvram);
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while (data & NVR_BUSY) {
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udelay(100);
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data = RD_REG_WORD(®->nvram);
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}
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/* Lock resource */
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WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1);
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RD_REG_WORD(®->u.isp2300.host_semaphore);
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udelay(5);
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data = RD_REG_WORD(®->u.isp2300.host_semaphore);
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while ((data & BIT_0) == 0) {
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/* Lock failed */
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udelay(100);
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WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1);
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RD_REG_WORD(®->u.isp2300.host_semaphore);
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udelay(5);
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data = RD_REG_WORD(®->u.isp2300.host_semaphore);
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}
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}
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}
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/**
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* qla2x00_unlock_nvram_access() -
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* @ha: HA context
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*/
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void
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qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
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{
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
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WRT_REG_WORD(®->u.isp2300.host_semaphore, 0);
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RD_REG_WORD(®->u.isp2300.host_semaphore);
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}
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}
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/**
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* qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
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* request routine to get the word from NVRAM.
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* @ha: HA context
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* @addr: Address in NVRAM to read
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*
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* Returns the word read from nvram @addr.
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*/
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uint16_t
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qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr)
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{
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uint16_t data;
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uint32_t nv_cmd;
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nv_cmd = addr << 16;
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nv_cmd |= NV_READ_OP;
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data = qla2x00_nvram_request(ha, nv_cmd);
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return (data);
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}
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/**
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* qla2x00_write_nvram_word() - Write NVRAM data.
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* @ha: HA context
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* @addr: Address in NVRAM to write
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* @data: word to program
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*/
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void
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qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
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{
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int count;
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uint16_t word;
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uint32_t nv_cmd;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_write(ha, 0);
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qla2x00_nv_write(ha, 0);
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for (word = 0; word < 8; word++)
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_deselect(ha);
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/* Write data */
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nv_cmd = (addr << 16) | NV_WRITE_OP;
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nv_cmd |= data;
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nv_cmd <<= 5;
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for (count = 0; count < 27; count++) {
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if (nv_cmd & BIT_31)
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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else
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qla2x00_nv_write(ha, 0);
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nv_cmd <<= 1;
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}
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qla2x00_nv_deselect(ha);
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/* Wait for NVRAM to become ready */
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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do {
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NVRAM_DELAY();
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word = RD_REG_WORD(®->nvram);
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} while ((word & NVR_DATA_IN) == 0);
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qla2x00_nv_deselect(ha);
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/* Disable writes */
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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for (count = 0; count < 10; count++)
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qla2x00_nv_write(ha, 0);
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qla2x00_nv_deselect(ha);
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}
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static int
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qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
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uint32_t tmo)
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{
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int ret, count;
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uint16_t word;
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uint32_t nv_cmd;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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ret = QLA_SUCCESS;
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_write(ha, 0);
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qla2x00_nv_write(ha, 0);
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for (word = 0; word < 8; word++)
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_deselect(ha);
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/* Write data */
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nv_cmd = (addr << 16) | NV_WRITE_OP;
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nv_cmd |= data;
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nv_cmd <<= 5;
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for (count = 0; count < 27; count++) {
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if (nv_cmd & BIT_31)
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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else
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qla2x00_nv_write(ha, 0);
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nv_cmd <<= 1;
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}
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qla2x00_nv_deselect(ha);
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/* Wait for NVRAM to become ready */
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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do {
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NVRAM_DELAY();
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word = RD_REG_WORD(®->nvram);
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if (!--tmo) {
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ret = QLA_FUNCTION_FAILED;
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break;
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}
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} while ((word & NVR_DATA_IN) == 0);
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qla2x00_nv_deselect(ha);
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/* Disable writes */
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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for (count = 0; count < 10; count++)
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qla2x00_nv_write(ha, 0);
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qla2x00_nv_deselect(ha);
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return ret;
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}
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/**
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* qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
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* NVRAM.
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* @ha: HA context
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* @nv_cmd: NVRAM command
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*
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* Bit definitions for NVRAM command:
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*
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* Bit 26 = start bit
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* Bit 25, 24 = opcode
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* Bit 23-16 = address
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* Bit 15-0 = write data
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*
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* Returns the word read from nvram @addr.
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*/
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static uint16_t
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qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
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{
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uint8_t cnt;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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uint16_t data = 0;
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uint16_t reg_data;
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/* Send command to NVRAM. */
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nv_cmd <<= 5;
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for (cnt = 0; cnt < 11; cnt++) {
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if (nv_cmd & BIT_31)
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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else
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qla2x00_nv_write(ha, 0);
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nv_cmd <<= 1;
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}
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/* Read data from NVRAM. */
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for (cnt = 0; cnt < 16; cnt++) {
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WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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NVRAM_DELAY();
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data <<= 1;
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reg_data = RD_REG_WORD(®->nvram);
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if (reg_data & NVR_DATA_IN)
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data |= BIT_0;
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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NVRAM_DELAY();
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}
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/* Deselect chip. */
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WRT_REG_WORD(®->nvram, NVR_DESELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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NVRAM_DELAY();
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return (data);
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}
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/**
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* qla2x00_nv_write() - Clean NVRAM operations.
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* @ha: HA context
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*/
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static void
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qla2x00_nv_deselect(scsi_qla_host_t *ha)
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{
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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WRT_REG_WORD(®->nvram, NVR_DESELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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NVRAM_DELAY();
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}
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/**
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* qla2x00_nv_write() - Prepare for NVRAM read/write operation.
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* @ha: HA context
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* @data: Serial interface selector
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*/
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static void
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qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
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{
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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NVRAM_DELAY();
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WRT_REG_WORD(®->nvram, data | NVR_SELECT| NVR_CLOCK |
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NVR_WRT_ENABLE);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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NVRAM_DELAY();
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WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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NVRAM_DELAY();
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}
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/**
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* qla2x00_clear_nvram_protection() -
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* @ha: HA context
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*/
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static int
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qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
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{
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int ret, stat;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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uint32_t word;
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uint16_t wprot, wprot_old;
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/* Clear NVRAM write protection. */
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ret = QLA_FUNCTION_FAILED;
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wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, 0));
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stat = qla2x00_write_nvram_word_tmo(ha, 0,
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__constant_cpu_to_le16(0x1234), 100000);
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wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, 0));
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if (stat != QLA_SUCCESS || wprot != __constant_cpu_to_le16(0x1234)) {
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/* Write enable. */
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_write(ha, 0);
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qla2x00_nv_write(ha, 0);
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for (word = 0; word < 8; word++)
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_deselect(ha);
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/* Enable protection register. */
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qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
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qla2x00_nv_write(ha, NVR_PR_ENABLE);
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qla2x00_nv_write(ha, NVR_PR_ENABLE);
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for (word = 0; word < 8; word++)
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qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
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qla2x00_nv_deselect(ha);
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/* Clear protection register (ffff is cleared). */
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qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
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qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
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qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
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for (word = 0; word < 8; word++)
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qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
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qla2x00_nv_deselect(ha);
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/* Wait for NVRAM to become ready. */
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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do {
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NVRAM_DELAY();
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word = RD_REG_WORD(®->nvram);
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} while ((word & NVR_DATA_IN) == 0);
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ret = QLA_SUCCESS;
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} else
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qla2x00_write_nvram_word(ha, 0, wprot_old);
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return ret;
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}
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static void
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qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
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{
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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uint32_t word;
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if (stat != QLA_SUCCESS)
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return;
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/* Set NVRAM write protection. */
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/* Write enable. */
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_write(ha, 0);
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qla2x00_nv_write(ha, 0);
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for (word = 0; word < 8; word++)
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_deselect(ha);
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/* Enable protection register. */
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qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
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qla2x00_nv_write(ha, NVR_PR_ENABLE);
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qla2x00_nv_write(ha, NVR_PR_ENABLE);
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for (word = 0; word < 8; word++)
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qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
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qla2x00_nv_deselect(ha);
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/* Enable protection register. */
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qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
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qla2x00_nv_write(ha, NVR_PR_ENABLE);
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qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
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for (word = 0; word < 8; word++)
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qla2x00_nv_write(ha, NVR_PR_ENABLE);
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qla2x00_nv_deselect(ha);
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/* Wait for NVRAM to become ready. */
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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do {
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NVRAM_DELAY();
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word = RD_REG_WORD(®->nvram);
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} while ((word & NVR_DATA_IN) == 0);
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}
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/*****************************************************************************/
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/* Flash Manipulation Routines */
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/*****************************************************************************/
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static inline uint32_t
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flash_conf_to_access_addr(uint32_t faddr)
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{
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return FARX_ACCESS_FLASH_CONF | faddr;
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}
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static inline uint32_t
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flash_data_to_access_addr(uint32_t faddr)
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{
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return FARX_ACCESS_FLASH_DATA | faddr;
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}
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static inline uint32_t
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nvram_conf_to_access_addr(uint32_t naddr)
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{
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return FARX_ACCESS_NVRAM_CONF | naddr;
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}
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static inline uint32_t
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nvram_data_to_access_addr(uint32_t naddr)
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{
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return FARX_ACCESS_NVRAM_DATA | naddr;
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}
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uint32_t
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qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr)
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{
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int rval;
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uint32_t cnt, data;
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struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
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WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG);
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/* Wait for READ cycle to complete. */
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rval = QLA_SUCCESS;
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for (cnt = 3000;
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(RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 &&
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rval == QLA_SUCCESS; cnt--) {
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if (cnt)
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udelay(10);
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else
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rval = QLA_FUNCTION_TIMEOUT;
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}
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/* TODO: What happens if we time out? */
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data = 0xDEADDEAD;
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if (rval == QLA_SUCCESS)
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data = RD_REG_DWORD(®->flash_data);
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return data;
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}
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uint32_t *
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qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
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uint32_t dwords)
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{
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uint32_t i;
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/* Dword reads to flash. */
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for (i = 0; i < dwords; i++, faddr++)
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dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
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flash_data_to_access_addr(faddr)));
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return dwptr;
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}
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int
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qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data)
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{
|
|
int rval;
|
|
uint32_t cnt;
|
|
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
|
|
|
|
WRT_REG_DWORD(®->flash_data, data);
|
|
RD_REG_DWORD(®->flash_data); /* PCI Posting. */
|
|
WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG);
|
|
/* Wait for Write cycle to complete. */
|
|
rval = QLA_SUCCESS;
|
|
for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) &&
|
|
rval == QLA_SUCCESS; cnt--) {
|
|
if (cnt)
|
|
udelay(10);
|
|
else
|
|
rval = QLA_FUNCTION_TIMEOUT;
|
|
}
|
|
return rval;
|
|
}
|
|
|
|
void
|
|
qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
|
|
uint8_t *flash_id)
|
|
{
|
|
uint32_t ids;
|
|
|
|
ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
|
|
*man_id = LSB(ids);
|
|
*flash_id = MSB(ids);
|
|
}
|
|
|
|
int
|
|
qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
|
|
uint32_t dwords)
|
|
{
|
|
int ret;
|
|
uint32_t liter;
|
|
uint32_t sec_mask, rest_addr, conf_addr;
|
|
uint32_t fdata;
|
|
uint8_t man_id, flash_id;
|
|
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
|
|
|
|
ret = QLA_SUCCESS;
|
|
|
|
qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
|
|
DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__,
|
|
ha->host_no, man_id, flash_id));
|
|
|
|
conf_addr = flash_conf_to_access_addr(0x03d8);
|
|
switch (man_id) {
|
|
case 0xbf: /* STT flash. */
|
|
rest_addr = 0x1fff;
|
|
sec_mask = 0x3e000;
|
|
if (flash_id == 0x80)
|
|
conf_addr = flash_conf_to_access_addr(0x0352);
|
|
break;
|
|
case 0x13: /* ST M25P80. */
|
|
rest_addr = 0x3fff;
|
|
sec_mask = 0x3c000;
|
|
break;
|
|
default:
|
|
/* Default to 64 kb sector size. */
|
|
rest_addr = 0x3fff;
|
|
sec_mask = 0x3c000;
|
|
break;
|
|
}
|
|
|
|
/* Enable flash write. */
|
|
WRT_REG_DWORD(®->ctrl_status,
|
|
RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
|
|
RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
|
|
|
|
/* Disable flash write-protection. */
|
|
qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
|
|
|
|
do { /* Loop once to provide quick error exit. */
|
|
for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
|
|
/* Are we at the beginning of a sector? */
|
|
if ((faddr & rest_addr) == 0) {
|
|
fdata = (faddr & sec_mask) << 2;
|
|
ret = qla24xx_write_flash_dword(ha, conf_addr,
|
|
(fdata & 0xff00) |((fdata << 16) &
|
|
0xff0000) | ((fdata >> 16) & 0xff));
|
|
if (ret != QLA_SUCCESS) {
|
|
DEBUG9(printk("%s(%ld) Unable to flash "
|
|
"sector: address=%x.\n", __func__,
|
|
ha->host_no, faddr));
|
|
break;
|
|
}
|
|
}
|
|
ret = qla24xx_write_flash_dword(ha,
|
|
flash_data_to_access_addr(faddr),
|
|
cpu_to_le32(*dwptr));
|
|
if (ret != QLA_SUCCESS) {
|
|
DEBUG9(printk("%s(%ld) Unable to program flash "
|
|
"address=%x data=%x.\n", __func__,
|
|
ha->host_no, faddr, *dwptr));
|
|
break;
|
|
}
|
|
}
|
|
} while (0);
|
|
|
|
/* Disable flash write. */
|
|
WRT_REG_DWORD(®->ctrl_status,
|
|
RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
|
|
RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
|
|
|
|
return ret;
|
|
}
|
|
|
|
uint8_t *
|
|
qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
|
|
uint32_t bytes)
|
|
{
|
|
uint32_t i;
|
|
uint16_t *wptr;
|
|
|
|
/* Word reads to NVRAM via registers. */
|
|
wptr = (uint16_t *)buf;
|
|
qla2x00_lock_nvram_access(ha);
|
|
for (i = 0; i < bytes >> 1; i++, naddr++)
|
|
wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
|
|
naddr));
|
|
qla2x00_unlock_nvram_access(ha);
|
|
|
|
return buf;
|
|
}
|
|
|
|
uint8_t *
|
|
qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
|
|
uint32_t bytes)
|
|
{
|
|
uint32_t i;
|
|
uint32_t *dwptr;
|
|
|
|
/* Dword reads to flash. */
|
|
dwptr = (uint32_t *)buf;
|
|
for (i = 0; i < bytes >> 2; i++, naddr++)
|
|
dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
|
|
nvram_data_to_access_addr(naddr)));
|
|
|
|
return buf;
|
|
}
|
|
|
|
int
|
|
qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
|
|
uint32_t bytes)
|
|
{
|
|
int ret, stat;
|
|
uint32_t i;
|
|
uint16_t *wptr;
|
|
|
|
ret = QLA_SUCCESS;
|
|
|
|
qla2x00_lock_nvram_access(ha);
|
|
|
|
/* Disable NVRAM write-protection. */
|
|
stat = qla2x00_clear_nvram_protection(ha);
|
|
|
|
wptr = (uint16_t *)buf;
|
|
for (i = 0; i < bytes >> 1; i++, naddr++) {
|
|
qla2x00_write_nvram_word(ha, naddr,
|
|
cpu_to_le16(*wptr));
|
|
wptr++;
|
|
}
|
|
|
|
/* Enable NVRAM write-protection. */
|
|
qla2x00_set_nvram_protection(ha, stat);
|
|
|
|
qla2x00_unlock_nvram_access(ha);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int
|
|
qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
|
|
uint32_t bytes)
|
|
{
|
|
int ret;
|
|
uint32_t i;
|
|
uint32_t *dwptr;
|
|
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
|
|
|
|
ret = QLA_SUCCESS;
|
|
|
|
/* Enable flash write. */
|
|
WRT_REG_DWORD(®->ctrl_status,
|
|
RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
|
|
RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
|
|
|
|
/* Disable NVRAM write-protection. */
|
|
qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
|
|
0);
|
|
qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
|
|
0);
|
|
|
|
/* Dword writes to flash. */
|
|
dwptr = (uint32_t *)buf;
|
|
for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
|
|
ret = qla24xx_write_flash_dword(ha,
|
|
nvram_data_to_access_addr(naddr),
|
|
cpu_to_le32(*dwptr));
|
|
if (ret != QLA_SUCCESS) {
|
|
DEBUG9(printk("%s(%ld) Unable to program "
|
|
"nvram address=%x data=%x.\n", __func__,
|
|
ha->host_no, naddr, *dwptr));
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Enable NVRAM write-protection. */
|
|
qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
|
|
0x8c);
|
|
|
|
/* Disable flash write. */
|
|
WRT_REG_DWORD(®->ctrl_status,
|
|
RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
|
|
RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
|
|
|
|
return ret;
|
|
}
|