6deb9bf458
The 600M clock in the fabric is not the real reference, replace it with a 125M clock which is the correct value for the icicle kit. Rename the msspllclk node to mssrefclk since this is now the input to, not the output of, the msspll clock. Control of the msspll clock has been moved into the clock configurator, so add the register range for it to the clk configurator. Finally, add a new output of the clock config block which will provide the 1M reference clock for the MTIMER and the rtc. Fixes:528a5b1f25("riscv: dts: microchip: add new peripherals to icicle kit device tree") Fixes:0fa6107eca("RISC-V: Initial DTS for Microchip ICICLE board") Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220413075835.3354193-10-conor.dooley@microchip.com Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
456 lines
11 KiB
Plaintext
456 lines
11 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020-2021 Microchip Technology Inc */
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/dts-v1/;
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#include "dt-bindings/clock/microchip,mpfs-clock.h"
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#include "microchip-mpfs-fabric.dtsi"
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "Microchip PolarFire SoC";
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compatible = "microchip,mpfs";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "sifive,e51", "sifive,rocket0", "riscv";
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <16384>;
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reg = <0>;
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riscv,isa = "rv64imac";
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clocks = <&clkcfg CLK_CPU>;
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status = "disabled";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu1: cpu@1 {
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <1>;
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riscv,isa = "rv64imafdc";
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clocks = <&clkcfg CLK_CPU>;
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tlb-split;
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status = "okay";
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu2: cpu@2 {
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <2>;
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riscv,isa = "rv64imafdc";
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clocks = <&clkcfg CLK_CPU>;
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tlb-split;
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status = "okay";
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cpu2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu3: cpu@3 {
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <3>;
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riscv,isa = "rv64imafdc";
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clocks = <&clkcfg CLK_CPU>;
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tlb-split;
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status = "okay";
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cpu3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu4: cpu@4 {
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <4>;
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riscv,isa = "rv64imafdc";
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clocks = <&clkcfg CLK_CPU>;
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tlb-split;
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status = "okay";
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cpu4_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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refclk: mssrefclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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cctrllr: cache-controller@2010000 {
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compatible = "sifive,fu540-c000-ccache", "cache";
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reg = <0x0 0x2010000 0x0 0x1000>;
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cache-block-size = <64>;
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cache-level = <2>;
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cache-sets = <1024>;
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cache-size = <2097152>;
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cache-unified;
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interrupt-parent = <&plic>;
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interrupts = <1>, <2>, <3>;
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};
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clint: clint@2000000 {
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compatible = "sifive,fu540-c000-clint", "sifive,clint0";
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reg = <0x0 0x2000000 0x0 0xC000>;
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interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
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<&cpu1_intc 3>, <&cpu1_intc 7>,
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<&cpu2_intc 3>, <&cpu2_intc 7>,
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<&cpu3_intc 3>, <&cpu3_intc 7>,
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<&cpu4_intc 3>, <&cpu4_intc 7>;
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};
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plic: interrupt-controller@c000000 {
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compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
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reg = <0x0 0xc000000 0x0 0x4000000>;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts-extended = <&cpu0_intc 11>,
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<&cpu1_intc 11>, <&cpu1_intc 9>,
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<&cpu2_intc 11>, <&cpu2_intc 9>,
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<&cpu3_intc 11>, <&cpu3_intc 9>,
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<&cpu4_intc 11>, <&cpu4_intc 9>;
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riscv,ndev = <186>;
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};
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clkcfg: clkcfg@20002000 {
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compatible = "microchip,mpfs-clkcfg";
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reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
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clocks = <&refclk>;
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#clock-cells = <1>;
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};
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mmuart0: serial@20000000 {
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compatible = "ns16550a";
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reg = <0x0 0x20000000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <90>;
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current-speed = <115200>;
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clocks = <&clkcfg CLK_MMUART0>;
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status = "disabled"; /* Reserved for the HSS */
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};
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mmuart1: serial@20100000 {
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compatible = "ns16550a";
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reg = <0x0 0x20100000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <91>;
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current-speed = <115200>;
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clocks = <&clkcfg CLK_MMUART1>;
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status = "disabled";
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};
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mmuart2: serial@20102000 {
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compatible = "ns16550a";
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reg = <0x0 0x20102000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <92>;
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current-speed = <115200>;
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clocks = <&clkcfg CLK_MMUART2>;
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status = "disabled";
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};
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mmuart3: serial@20104000 {
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compatible = "ns16550a";
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reg = <0x0 0x20104000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <93>;
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current-speed = <115200>;
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clocks = <&clkcfg CLK_MMUART3>;
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status = "disabled";
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};
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mmuart4: serial@20106000 {
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compatible = "ns16550a";
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reg = <0x0 0x20106000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <94>;
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clocks = <&clkcfg CLK_MMUART4>;
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current-speed = <115200>;
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status = "disabled";
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};
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/* Common node entry for emmc/sd */
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mmc: mmc@20008000 {
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compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
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reg = <0x0 0x20008000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <88>;
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clocks = <&clkcfg CLK_MMC>;
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max-frequency = <200000000>;
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status = "disabled";
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};
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spi0: spi@20108000 {
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compatible = "microchip,mpfs-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x20108000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <54>;
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clocks = <&clkcfg CLK_SPI0>;
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spi-max-frequency = <25000000>;
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status = "disabled";
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};
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spi1: spi@20109000 {
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compatible = "microchip,mpfs-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x20109000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <55>;
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clocks = <&clkcfg CLK_SPI1>;
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spi-max-frequency = <25000000>;
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status = "disabled";
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};
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qspi: spi@21000000 {
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compatible = "microchip,mpfs-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x21000000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <85>;
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clocks = <&clkcfg CLK_QSPI>;
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spi-max-frequency = <25000000>;
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status = "disabled";
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};
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i2c0: i2c@2010a000 {
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compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
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reg = <0x0 0x2010a000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&plic>;
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interrupts = <58>;
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clocks = <&clkcfg CLK_I2C0>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c1: i2c@2010b000 {
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compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
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reg = <0x0 0x2010b000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&plic>;
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interrupts = <61>;
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clocks = <&clkcfg CLK_I2C1>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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mac0: ethernet@20110000 {
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compatible = "cdns,macb";
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reg = <0x0 0x20110000 0x0 0x2000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&plic>;
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interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
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local-mac-address = [00 00 00 00 00 00];
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clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
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clock-names = "pclk", "hclk";
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status = "disabled";
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};
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mac1: ethernet@20112000 {
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compatible = "cdns,macb";
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reg = <0x0 0x20112000 0x0 0x2000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&plic>;
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interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
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local-mac-address = [00 00 00 00 00 00];
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clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
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clock-names = "pclk", "hclk";
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status = "disabled";
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};
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gpio0: gpio@20120000 {
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compatible = "microchip,mpfs-gpio";
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reg = <0x0 0x20120000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupt-controller;
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#interrupt-cells = <1>;
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clocks = <&clkcfg CLK_GPIO0>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio1: gpio@20121000 {
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compatible = "microchip,mpfs-gpio";
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reg = <000 0x20121000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupt-controller;
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#interrupt-cells = <1>;
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clocks = <&clkcfg CLK_GPIO1>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio2: gpio@20122000 {
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compatible = "microchip,mpfs-gpio";
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reg = <0x0 0x20122000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupt-controller;
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#interrupt-cells = <1>;
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clocks = <&clkcfg CLK_GPIO2>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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rtc: rtc@20124000 {
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compatible = "microchip,mpfs-rtc";
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reg = <0x0 0x20124000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <80>, <81>;
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clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
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clock-names = "rtc", "rtcref";
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status = "disabled";
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};
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usb: usb@20201000 {
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compatible = "microchip,mpfs-musb";
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reg = <0x0 0x20201000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <86>, <87>;
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clocks = <&clkcfg CLK_USB>;
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interrupt-names = "dma","mc";
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status = "disabled";
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};
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pcie: pcie@2000000000 {
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compatible = "microchip,pcie-host-1.0";
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#address-cells = <0x3>;
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#interrupt-cells = <0x1>;
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#size-cells = <0x2>;
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device_type = "pci";
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reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
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reg-names = "cfg", "apb";
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bus-range = <0x0 0x7f>;
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interrupt-parent = <&plic>;
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interrupts = <119>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>,
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<0 0 0 2 &pcie_intc 1>,
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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interrupt-map-mask = <0 0 0 7>;
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clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
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clock-names = "fic0", "fic1", "fic3";
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ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
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msi-parent = <&pcie>;
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msi-controller;
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microchip,axi-m-atr0 = <0x10 0x0>;
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status = "disabled";
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pcie_intc: legacy-interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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mbox: mailbox@37020000 {
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compatible = "microchip,mpfs-mailbox";
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reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
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interrupt-parent = <&plic>;
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interrupts = <96>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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syscontroller: syscontroller {
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compatible = "microchip,mpfs-sys-controller";
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mboxes = <&mbox 0>;
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};
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};
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};
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