2b6190c804
The fic clocks passed to the pcie controller and other peripherals in
the device tree are not the clocks they actually run on. The fics are
actually clock domain crossers & the clock config blocks output is the
mss/cpu side input to the interconnect. The peripherals are actually
clocked by fixed frequency clocks embedded in the fpga fabric.
Fix the device tree so that these peripherals use the correct clocks.
The fabric side FIC0 & FIC1 inputs both use the same 125 MHz, so only
one clock is created for them.
Fixes: 528a5b1f25 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220413075835.3354193-4-conor.dooley@microchip.com
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
38 lines
852 B
Plaintext
38 lines
852 B
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020-2021 Microchip Technology Inc */
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/ {
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core_pwm0: pwm@41000000 {
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compatible = "microchip,corepwm-rtl-v4";
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reg = <0x0 0x41000000 0x0 0xF0>;
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microchip,sync-update-mask = /bits/ 32 <0>;
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#pwm-cells = <2>;
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clocks = <&fabric_clk3>;
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status = "disabled";
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};
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i2c2: i2c@44000000 {
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compatible = "microchip,corei2c-rtl-v7";
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reg = <0x0 0x44000000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&fabric_clk3>;
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interrupt-parent = <&plic>;
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interrupts = <122>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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fabric_clk3: fabric-clk3 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <62500000>;
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};
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fabric_clk1: fabric-clk1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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};
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