53126a2f67
s/Synopsis/Synopsys s/synopsis/synopsys Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> CC: Arnd Bergmann <arnd@arndb.de> CC: Olof Johansson <olof@lixom.net> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Ian Campbell <ian.campbell@citrix.com> Cc: Chris Ball <cjb@laptop.org> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Seungwon Jeon <tgih.jun@samsung.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: devicetree@vger.kernel.org Cc: linux-mmc@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
77 lines
2.4 KiB
Plaintext
77 lines
2.4 KiB
Plaintext
* Synopsys Designware PCIe interface
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Required properties:
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- compatible: should contain "snps,dw-pcie" to identify the
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core, plus an identifier for the specific instance, such
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as "samsung,exynos5440-pcie".
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- reg: base addresses and lengths of the pcie controller,
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the phy controller, additional register for the phy controller.
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- interrupts: interrupt values for level interrupt,
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pulse interrupt, special interrupt.
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- clocks: from common clock binding: handle to pci clock.
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- clock-names: from common clock binding: should be "pcie" and "pcie_bus".
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- device_type: set to "pci"
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- ranges: ranges for the PCI memory and I/O regions
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- #interrupt-cells: set to <1>
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- interrupt-map-mask and interrupt-map: standard PCI properties
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to define the mapping of the PCIe interface to interrupt
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numbers.
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- num-lanes: number of lanes to use
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- reset-gpio: gpio pin number of power good signal
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Example:
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SoC specific DT Entry:
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pcie@290000 {
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compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
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reg = <0x290000 0x1000
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0x270000 0x1000
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0x271000 0x40>;
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interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
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clocks = <&clock 28>, <&clock 27>;
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clock-names = "pcie", "pcie_bus";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
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0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0x0 0 &gic 53>;
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num-lanes = <4>;
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};
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pcie@2a0000 {
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compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
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reg = <0x2a0000 0x1000
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0x272000 0x1000
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0x271040 0x40>;
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interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
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clocks = <&clock 29>, <&clock 27>;
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clock-names = "pcie", "pcie_bus";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
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0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0x0 0 &gic 56>;
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num-lanes = <4>;
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};
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Board specific DT Entry:
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pcie@290000 {
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reset-gpio = <&pin_ctrl 5 0>;
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};
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pcie@2a0000 {
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reset-gpio = <&pin_ctrl 22 0>;
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};
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