forked from Minki/linux
6dfacadd58
We can easily emulate the HLT activity state for L1: If it decides that L2 shall be halted on entry, just invoke the normal emulation of halt after switching to L2. We do not depend on specific host features to provide this, so we can expose the capability unconditionally. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
481 lines
20 KiB
C
481 lines
20 KiB
C
/*
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* vmx.h: VMX Architecture related definitions
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* Copyright (c) 2004, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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* A few random additions are:
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* Copyright (C) 2006 Qumranet
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* Avi Kivity <avi@qumranet.com>
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* Yaniv Kamay <yaniv@qumranet.com>
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*
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*/
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#ifndef VMX_H
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#define VMX_H
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#include <linux/types.h>
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#include <uapi/asm/vmx.h>
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/*
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* Definitions of Primary Processor-Based VM-Execution Controls.
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*/
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#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
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#define CPU_BASED_USE_TSC_OFFSETING 0x00000008
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#define CPU_BASED_HLT_EXITING 0x00000080
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#define CPU_BASED_INVLPG_EXITING 0x00000200
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#define CPU_BASED_MWAIT_EXITING 0x00000400
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#define CPU_BASED_RDPMC_EXITING 0x00000800
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#define CPU_BASED_RDTSC_EXITING 0x00001000
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#define CPU_BASED_CR3_LOAD_EXITING 0x00008000
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#define CPU_BASED_CR3_STORE_EXITING 0x00010000
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#define CPU_BASED_CR8_LOAD_EXITING 0x00080000
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#define CPU_BASED_CR8_STORE_EXITING 0x00100000
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#define CPU_BASED_TPR_SHADOW 0x00200000
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#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
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#define CPU_BASED_MOV_DR_EXITING 0x00800000
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#define CPU_BASED_UNCOND_IO_EXITING 0x01000000
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#define CPU_BASED_USE_IO_BITMAPS 0x02000000
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#define CPU_BASED_USE_MSR_BITMAPS 0x10000000
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#define CPU_BASED_MONITOR_EXITING 0x20000000
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#define CPU_BASED_PAUSE_EXITING 0x40000000
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#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
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/*
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* Definitions of Secondary Processor-Based VM-Execution Controls.
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*/
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#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
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#define SECONDARY_EXEC_ENABLE_EPT 0x00000002
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#define SECONDARY_EXEC_RDTSCP 0x00000008
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#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
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#define SECONDARY_EXEC_ENABLE_VPID 0x00000020
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#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
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#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
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#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
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#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
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#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
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#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
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#define SECONDARY_EXEC_SHADOW_VMCS 0x00004000
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#define PIN_BASED_EXT_INTR_MASK 0x00000001
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#define PIN_BASED_NMI_EXITING 0x00000008
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#define PIN_BASED_VIRTUAL_NMIS 0x00000020
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#define PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
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#define PIN_BASED_POSTED_INTR 0x00000080
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#define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016
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#define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000002
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#define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
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#define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
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#define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
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#define VM_EXIT_SAVE_IA32_PAT 0x00040000
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#define VM_EXIT_LOAD_IA32_PAT 0x00080000
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#define VM_EXIT_SAVE_IA32_EFER 0x00100000
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#define VM_EXIT_LOAD_IA32_EFER 0x00200000
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#define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
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#define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff
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#define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000002
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#define VM_ENTRY_IA32E_MODE 0x00000200
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#define VM_ENTRY_SMM 0x00000400
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#define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
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#define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
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#define VM_ENTRY_LOAD_IA32_PAT 0x00004000
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#define VM_ENTRY_LOAD_IA32_EFER 0x00008000
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#define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff
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#define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f
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#define VMX_MISC_SAVE_EFER_LMA 0x00000020
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#define VMX_MISC_ACTIVITY_HLT 0x00000040
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/* VMCS Encodings */
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enum vmcs_field {
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VIRTUAL_PROCESSOR_ID = 0x00000000,
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POSTED_INTR_NV = 0x00000002,
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GUEST_ES_SELECTOR = 0x00000800,
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GUEST_CS_SELECTOR = 0x00000802,
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GUEST_SS_SELECTOR = 0x00000804,
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GUEST_DS_SELECTOR = 0x00000806,
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GUEST_FS_SELECTOR = 0x00000808,
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GUEST_GS_SELECTOR = 0x0000080a,
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GUEST_LDTR_SELECTOR = 0x0000080c,
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GUEST_TR_SELECTOR = 0x0000080e,
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GUEST_INTR_STATUS = 0x00000810,
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HOST_ES_SELECTOR = 0x00000c00,
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HOST_CS_SELECTOR = 0x00000c02,
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HOST_SS_SELECTOR = 0x00000c04,
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HOST_DS_SELECTOR = 0x00000c06,
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HOST_FS_SELECTOR = 0x00000c08,
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HOST_GS_SELECTOR = 0x00000c0a,
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HOST_TR_SELECTOR = 0x00000c0c,
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IO_BITMAP_A = 0x00002000,
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IO_BITMAP_A_HIGH = 0x00002001,
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IO_BITMAP_B = 0x00002002,
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IO_BITMAP_B_HIGH = 0x00002003,
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MSR_BITMAP = 0x00002004,
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MSR_BITMAP_HIGH = 0x00002005,
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VM_EXIT_MSR_STORE_ADDR = 0x00002006,
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VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
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VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
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VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
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VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
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VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
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TSC_OFFSET = 0x00002010,
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TSC_OFFSET_HIGH = 0x00002011,
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VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
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VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
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APIC_ACCESS_ADDR = 0x00002014,
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APIC_ACCESS_ADDR_HIGH = 0x00002015,
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POSTED_INTR_DESC_ADDR = 0x00002016,
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POSTED_INTR_DESC_ADDR_HIGH = 0x00002017,
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EPT_POINTER = 0x0000201a,
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EPT_POINTER_HIGH = 0x0000201b,
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EOI_EXIT_BITMAP0 = 0x0000201c,
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EOI_EXIT_BITMAP0_HIGH = 0x0000201d,
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EOI_EXIT_BITMAP1 = 0x0000201e,
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EOI_EXIT_BITMAP1_HIGH = 0x0000201f,
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EOI_EXIT_BITMAP2 = 0x00002020,
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EOI_EXIT_BITMAP2_HIGH = 0x00002021,
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EOI_EXIT_BITMAP3 = 0x00002022,
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EOI_EXIT_BITMAP3_HIGH = 0x00002023,
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VMREAD_BITMAP = 0x00002026,
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VMWRITE_BITMAP = 0x00002028,
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GUEST_PHYSICAL_ADDRESS = 0x00002400,
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GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
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VMCS_LINK_POINTER = 0x00002800,
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VMCS_LINK_POINTER_HIGH = 0x00002801,
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GUEST_IA32_DEBUGCTL = 0x00002802,
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GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
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GUEST_IA32_PAT = 0x00002804,
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GUEST_IA32_PAT_HIGH = 0x00002805,
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GUEST_IA32_EFER = 0x00002806,
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GUEST_IA32_EFER_HIGH = 0x00002807,
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GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
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GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
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GUEST_PDPTR0 = 0x0000280a,
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GUEST_PDPTR0_HIGH = 0x0000280b,
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GUEST_PDPTR1 = 0x0000280c,
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GUEST_PDPTR1_HIGH = 0x0000280d,
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GUEST_PDPTR2 = 0x0000280e,
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GUEST_PDPTR2_HIGH = 0x0000280f,
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GUEST_PDPTR3 = 0x00002810,
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GUEST_PDPTR3_HIGH = 0x00002811,
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HOST_IA32_PAT = 0x00002c00,
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HOST_IA32_PAT_HIGH = 0x00002c01,
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HOST_IA32_EFER = 0x00002c02,
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HOST_IA32_EFER_HIGH = 0x00002c03,
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HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
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HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
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PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
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CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
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EXCEPTION_BITMAP = 0x00004004,
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PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
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PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
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CR3_TARGET_COUNT = 0x0000400a,
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VM_EXIT_CONTROLS = 0x0000400c,
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VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
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VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
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VM_ENTRY_CONTROLS = 0x00004012,
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VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
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VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
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VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
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VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
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TPR_THRESHOLD = 0x0000401c,
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SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
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PLE_GAP = 0x00004020,
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PLE_WINDOW = 0x00004022,
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VM_INSTRUCTION_ERROR = 0x00004400,
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VM_EXIT_REASON = 0x00004402,
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VM_EXIT_INTR_INFO = 0x00004404,
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VM_EXIT_INTR_ERROR_CODE = 0x00004406,
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IDT_VECTORING_INFO_FIELD = 0x00004408,
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IDT_VECTORING_ERROR_CODE = 0x0000440a,
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VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
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VMX_INSTRUCTION_INFO = 0x0000440e,
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GUEST_ES_LIMIT = 0x00004800,
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GUEST_CS_LIMIT = 0x00004802,
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GUEST_SS_LIMIT = 0x00004804,
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GUEST_DS_LIMIT = 0x00004806,
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GUEST_FS_LIMIT = 0x00004808,
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GUEST_GS_LIMIT = 0x0000480a,
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GUEST_LDTR_LIMIT = 0x0000480c,
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GUEST_TR_LIMIT = 0x0000480e,
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GUEST_GDTR_LIMIT = 0x00004810,
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GUEST_IDTR_LIMIT = 0x00004812,
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GUEST_ES_AR_BYTES = 0x00004814,
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GUEST_CS_AR_BYTES = 0x00004816,
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GUEST_SS_AR_BYTES = 0x00004818,
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GUEST_DS_AR_BYTES = 0x0000481a,
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GUEST_FS_AR_BYTES = 0x0000481c,
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GUEST_GS_AR_BYTES = 0x0000481e,
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GUEST_LDTR_AR_BYTES = 0x00004820,
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GUEST_TR_AR_BYTES = 0x00004822,
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GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
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GUEST_ACTIVITY_STATE = 0X00004826,
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GUEST_SYSENTER_CS = 0x0000482A,
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VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
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HOST_IA32_SYSENTER_CS = 0x00004c00,
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CR0_GUEST_HOST_MASK = 0x00006000,
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CR4_GUEST_HOST_MASK = 0x00006002,
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CR0_READ_SHADOW = 0x00006004,
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CR4_READ_SHADOW = 0x00006006,
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CR3_TARGET_VALUE0 = 0x00006008,
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CR3_TARGET_VALUE1 = 0x0000600a,
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CR3_TARGET_VALUE2 = 0x0000600c,
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CR3_TARGET_VALUE3 = 0x0000600e,
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EXIT_QUALIFICATION = 0x00006400,
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GUEST_LINEAR_ADDRESS = 0x0000640a,
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GUEST_CR0 = 0x00006800,
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GUEST_CR3 = 0x00006802,
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GUEST_CR4 = 0x00006804,
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GUEST_ES_BASE = 0x00006806,
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GUEST_CS_BASE = 0x00006808,
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GUEST_SS_BASE = 0x0000680a,
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GUEST_DS_BASE = 0x0000680c,
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GUEST_FS_BASE = 0x0000680e,
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GUEST_GS_BASE = 0x00006810,
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GUEST_LDTR_BASE = 0x00006812,
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GUEST_TR_BASE = 0x00006814,
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GUEST_GDTR_BASE = 0x00006816,
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GUEST_IDTR_BASE = 0x00006818,
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GUEST_DR7 = 0x0000681a,
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GUEST_RSP = 0x0000681c,
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GUEST_RIP = 0x0000681e,
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GUEST_RFLAGS = 0x00006820,
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GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
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GUEST_SYSENTER_ESP = 0x00006824,
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GUEST_SYSENTER_EIP = 0x00006826,
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HOST_CR0 = 0x00006c00,
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HOST_CR3 = 0x00006c02,
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HOST_CR4 = 0x00006c04,
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HOST_FS_BASE = 0x00006c06,
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HOST_GS_BASE = 0x00006c08,
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HOST_TR_BASE = 0x00006c0a,
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HOST_GDTR_BASE = 0x00006c0c,
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HOST_IDTR_BASE = 0x00006c0e,
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HOST_IA32_SYSENTER_ESP = 0x00006c10,
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HOST_IA32_SYSENTER_EIP = 0x00006c12,
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HOST_RSP = 0x00006c14,
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HOST_RIP = 0x00006c16,
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};
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/*
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* Interruption-information format
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*/
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#define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
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#define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
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#define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
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#define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */
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#define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
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#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
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#define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK
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#define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK
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#define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK
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#define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK
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#define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
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#define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */
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#define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */
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#define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */
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#define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */
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/* GUEST_INTERRUPTIBILITY_INFO flags. */
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#define GUEST_INTR_STATE_STI 0x00000001
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#define GUEST_INTR_STATE_MOV_SS 0x00000002
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#define GUEST_INTR_STATE_SMI 0x00000004
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#define GUEST_INTR_STATE_NMI 0x00000008
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/* GUEST_ACTIVITY_STATE flags */
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#define GUEST_ACTIVITY_ACTIVE 0
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#define GUEST_ACTIVITY_HLT 1
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#define GUEST_ACTIVITY_SHUTDOWN 2
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#define GUEST_ACTIVITY_WAIT_SIPI 3
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/*
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* Exit Qualifications for MOV for Control Register Access
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*/
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#define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/
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#define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
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#define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */
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#define LMSW_SOURCE_DATA_SHIFT 16
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#define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
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#define REG_EAX (0 << 8)
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#define REG_ECX (1 << 8)
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#define REG_EDX (2 << 8)
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#define REG_EBX (3 << 8)
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#define REG_ESP (4 << 8)
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#define REG_EBP (5 << 8)
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#define REG_ESI (6 << 8)
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#define REG_EDI (7 << 8)
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#define REG_R8 (8 << 8)
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#define REG_R9 (9 << 8)
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#define REG_R10 (10 << 8)
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#define REG_R11 (11 << 8)
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#define REG_R12 (12 << 8)
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#define REG_R13 (13 << 8)
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#define REG_R14 (14 << 8)
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#define REG_R15 (15 << 8)
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/*
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* Exit Qualifications for MOV for Debug Register Access
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*/
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#define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */
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#define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
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#define TYPE_MOV_TO_DR (0 << 4)
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#define TYPE_MOV_FROM_DR (1 << 4)
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#define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
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/*
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* Exit Qualifications for APIC-Access
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*/
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#define APIC_ACCESS_OFFSET 0xfff /* 11:0, offset within the APIC page */
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#define APIC_ACCESS_TYPE 0xf000 /* 15:12, access type */
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#define TYPE_LINEAR_APIC_INST_READ (0 << 12)
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#define TYPE_LINEAR_APIC_INST_WRITE (1 << 12)
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#define TYPE_LINEAR_APIC_INST_FETCH (2 << 12)
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#define TYPE_LINEAR_APIC_EVENT (3 << 12)
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#define TYPE_PHYSICAL_APIC_EVENT (10 << 12)
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#define TYPE_PHYSICAL_APIC_INST (15 << 12)
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/* segment AR */
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#define SEGMENT_AR_L_MASK (1 << 13)
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#define AR_TYPE_ACCESSES_MASK 1
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#define AR_TYPE_READABLE_MASK (1 << 1)
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#define AR_TYPE_WRITEABLE_MASK (1 << 2)
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#define AR_TYPE_CODE_MASK (1 << 3)
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#define AR_TYPE_MASK 0x0f
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#define AR_TYPE_BUSY_64_TSS 11
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#define AR_TYPE_BUSY_32_TSS 11
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#define AR_TYPE_BUSY_16_TSS 3
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#define AR_TYPE_LDT 2
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#define AR_UNUSABLE_MASK (1 << 16)
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#define AR_S_MASK (1 << 4)
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#define AR_P_MASK (1 << 7)
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#define AR_L_MASK (1 << 13)
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#define AR_DB_MASK (1 << 14)
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#define AR_G_MASK (1 << 15)
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#define AR_DPL_SHIFT 5
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#define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
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#define AR_RESERVD_MASK 0xfffe0f00
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#define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0)
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#define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 1)
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#define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 2)
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#define VMX_NR_VPIDS (1 << 16)
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#define VMX_VPID_EXTENT_SINGLE_CONTEXT 1
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#define VMX_VPID_EXTENT_ALL_CONTEXT 2
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#define VMX_EPT_EXTENT_INDIVIDUAL_ADDR 0
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#define VMX_EPT_EXTENT_CONTEXT 1
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#define VMX_EPT_EXTENT_GLOBAL 2
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#define VMX_EPT_EXTENT_SHIFT 24
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#define VMX_EPT_EXECUTE_ONLY_BIT (1ull)
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#define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6)
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#define VMX_EPTP_UC_BIT (1ull << 8)
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#define VMX_EPTP_WB_BIT (1ull << 14)
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#define VMX_EPT_2MB_PAGE_BIT (1ull << 16)
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#define VMX_EPT_1GB_PAGE_BIT (1ull << 17)
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#define VMX_EPT_INVEPT_BIT (1ull << 20)
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#define VMX_EPT_AD_BIT (1ull << 21)
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#define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25)
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#define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26)
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#define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9) /* (41 - 32) */
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#define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10) /* (42 - 32) */
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#define VMX_EPT_DEFAULT_GAW 3
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#define VMX_EPT_MAX_GAW 0x4
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#define VMX_EPT_MT_EPTE_SHIFT 3
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#define VMX_EPT_GAW_EPTP_SHIFT 3
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#define VMX_EPT_AD_ENABLE_BIT (1ull << 6)
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#define VMX_EPT_DEFAULT_MT 0x6ull
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#define VMX_EPT_READABLE_MASK 0x1ull
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#define VMX_EPT_WRITABLE_MASK 0x2ull
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#define VMX_EPT_EXECUTABLE_MASK 0x4ull
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#define VMX_EPT_IPAT_BIT (1ull << 6)
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#define VMX_EPT_ACCESS_BIT (1ull << 8)
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#define VMX_EPT_DIRTY_BIT (1ull << 9)
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#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
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#define ASM_VMX_VMCLEAR_RAX ".byte 0x66, 0x0f, 0xc7, 0x30"
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#define ASM_VMX_VMLAUNCH ".byte 0x0f, 0x01, 0xc2"
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#define ASM_VMX_VMRESUME ".byte 0x0f, 0x01, 0xc3"
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#define ASM_VMX_VMPTRLD_RAX ".byte 0x0f, 0xc7, 0x30"
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#define ASM_VMX_VMREAD_RDX_RAX ".byte 0x0f, 0x78, 0xd0"
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#define ASM_VMX_VMWRITE_RAX_RDX ".byte 0x0f, 0x79, 0xd0"
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#define ASM_VMX_VMWRITE_RSP_RDX ".byte 0x0f, 0x79, 0xd4"
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#define ASM_VMX_VMXOFF ".byte 0x0f, 0x01, 0xc4"
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#define ASM_VMX_VMXON_RAX ".byte 0xf3, 0x0f, 0xc7, 0x30"
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#define ASM_VMX_INVEPT ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
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#define ASM_VMX_INVVPID ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
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struct vmx_msr_entry {
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u32 index;
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|
u32 reserved;
|
|
u64 value;
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} __aligned(16);
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|
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/*
|
|
* Exit Qualifications for entry failure during or after loading guest state
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|
*/
|
|
#define ENTRY_FAIL_DEFAULT 0
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#define ENTRY_FAIL_PDPTE 2
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#define ENTRY_FAIL_NMI 3
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#define ENTRY_FAIL_VMCS_LINK_PTR 4
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|
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/*
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* VM-instruction error numbers
|
|
*/
|
|
enum vm_instruction_error_number {
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VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
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|
VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
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|
VMXERR_VMCLEAR_VMXON_POINTER = 3,
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VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
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VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
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|
VMXERR_VMRESUME_AFTER_VMXOFF = 6,
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VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
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|
VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
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|
VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
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|
VMXERR_VMPTRLD_VMXON_POINTER = 10,
|
|
VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
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|
VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
|
|
VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
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|
VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
|
|
VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
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|
VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
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|
VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
|
|
VMXERR_VMCALL_NONCLEAR_VMCS = 19,
|
|
VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
|
|
VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
|
|
VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
|
|
VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
|
|
VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
|
|
VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
|
|
VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
|
|
};
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#endif
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