Jim Lodes 4bafcbc77f OMAPDSS: HDMI5: Change DDC timings ... The DDC scl high and low times were set to the minimum values from the i2c specification, but the i2c specification takes into account the rise time and fall time to calculate the frequency. To pass HDMI certification DDC can not exceed 100kHz therefore in a system where the rise times and fall times are negligible the high and low times for scl need to be 10us. Signed-off-by: Jim Lodes <jim.lodes@garmin.com> Signed-off-by: J.D. Schroeder <jay.schroeder@garmin.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>		2016-05-31 08:20:43 +03:00
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backlight	pwm: Changes for v4.7-rc1	2016-05-25 10:40:15 -07:00
console	tty: vt, make color_table const	2016-04-30 09:26:55 -07:00
fbdev	OMAPDSS: HDMI5: Change DDC timings	2016-05-31 08:20:43 +03:00
logo
display_timing.c
hdmi.c
Kconfig	fbdev: sh_mipi_dsi: remove driver	2016-05-10 11:53:38 +03:00
Makefile
of_display_timing.c	video: of: fix memory leak	2015-10-07 14:13:59 +03:00
of_videomode.c
vgastate.c
videomode.c