c5a4484941
when bit14 in module parameter ppfeaturemask was set. od feature will be enabled on Vega10 except vbios not support. user can read od range by reading sysfs pp_od_clk_voltage, cat pp_od_clk_voltage OD_SCLK: 0: 852Mhz 800mV 1: 991Mhz 900mV 2: 1138Mhz 950mV 3: 1269Mhz 1000mV 4: 1348Mhz 1050mV 5: 1399Mhz 1100mV 6: 1440Mhz 1150mV 7: 1500Mhz 1200mV OD_MCLK: 0: 167Mhz 800mV 1: 500Mhz 800mV 2: 800Mhz 950mV 3: 945Mhz 1000mV OD_RANGE: SCLK: 852MHz 2200MHz MCLK: 167MHz 1500MHz VDDC: 800mV 1200mV and can configure the clock/voltage by writing pp_od_clk_voltage for example: echo "s 0 900 820">pp_od_clk_voltage to change the sclk/vddc to 900MHz and 820 mV in dpm level0. echo "r" to change the clk/voltage to default value. echo "c">pp_od_clk_voltage to commit the change v2: squash in warning fix (Alex) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
||
---|---|---|
.. | ||
vega12 | ||
amd_powerplay.h | ||
cz_ppsmc.h | ||
fiji_ppsmc.h | ||
hardwaremanager.h | ||
hwmgr.h | ||
polaris10_pwrvirus.h | ||
power_state.h | ||
pp_debug.h | ||
pp_endian.h | ||
pp_power_source.h | ||
pp_thermal.h | ||
ppinterrupt.h | ||
rv_ppsmc.h | ||
smu7_common.h | ||
smu7_discrete.h | ||
smu7_fusion.h | ||
smu7_ppsmc.h | ||
smu7.h | ||
smu8_fusion.h | ||
smu8.h | ||
smu9_driver_if.h | ||
smu9.h | ||
smu10_driver_if.h | ||
smu10.h | ||
smu71_discrete.h | ||
smu71.h | ||
smu72_discrete.h | ||
smu72.h | ||
smu73_discrete.h | ||
smu73.h | ||
smu74_discrete.h | ||
smu74.h | ||
smu_ucode_xfer_cz.h | ||
smu_ucode_xfer_vi.h | ||
smumgr.h | ||
tonga_ppsmc.h | ||
vega10_ppsmc.h | ||
vega12_ppsmc.h |