eba7e6c6e5
Commit 5db7e3bb87 ("pinctrl: dt-bindings: samsung: Add header with
values used for configuration") has added a header file for defining the
pinctrl values in order to avoid hardcoded settings in the Exynos
DTS related files.
Extend samsung.h to the Exynos5433 for drive strength values
which are strictly related to the particular SoC and may defer
from others.
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
72 lines
2.1 KiB
C
72 lines
2.1 KiB
C
/*
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* Samsung's Exynos pinctrl bindings
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*
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* Copyright (c) 2016 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Author: Krzysztof Kozlowski <krzk@kernel.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__
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#define __DT_BINDINGS_PINCTRL_SAMSUNG_H__
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#define EXYNOS_PIN_PULL_NONE 0
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#define EXYNOS_PIN_PULL_DOWN 1
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#define EXYNOS_PIN_PULL_UP 3
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#define S3C64XX_PIN_PULL_NONE 0
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#define S3C64XX_PIN_PULL_DOWN 1
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#define S3C64XX_PIN_PULL_UP 2
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/* Pin function in power down mode */
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#define EXYNOS_PIN_PDN_OUT0 0
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#define EXYNOS_PIN_PDN_OUT1 1
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#define EXYNOS_PIN_PDN_INPUT 2
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#define EXYNOS_PIN_PDN_PREV 3
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/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */
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#define EXYNOS4_PIN_DRV_LV1 0
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#define EXYNOS4_PIN_DRV_LV2 2
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#define EXYNOS4_PIN_DRV_LV3 1
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#define EXYNOS4_PIN_DRV_LV4 3
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/* Drive strengths for Exynos5260 */
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#define EXYNOS5260_PIN_DRV_LV1 0
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#define EXYNOS5260_PIN_DRV_LV2 1
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#define EXYNOS5260_PIN_DRV_LV4 2
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#define EXYNOS5260_PIN_DRV_LV6 3
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/* Drive strengths for Exynos5410, Exynos542x and Exynos5800 */
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#define EXYNOS5420_PIN_DRV_LV1 0
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#define EXYNOS5420_PIN_DRV_LV2 1
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#define EXYNOS5420_PIN_DRV_LV3 2
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#define EXYNOS5420_PIN_DRV_LV4 3
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/* Drive strengths for Exynos5433 */
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#define EXYNOS5433_PIN_DRV_FAST_SR1 0
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#define EXYNOS5433_PIN_DRV_FAST_SR2 1
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#define EXYNOS5433_PIN_DRV_FAST_SR3 2
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#define EXYNOS5433_PIN_DRV_FAST_SR4 3
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#define EXYNOS5433_PIN_DRV_FAST_SR5 4
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#define EXYNOS5433_PIN_DRV_FAST_SR6 5
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#define EXYNOS5433_PIN_DRV_SLOW_SR1 8
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#define EXYNOS5433_PIN_DRV_SLOW_SR2 9
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#define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa
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#define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb
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#define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc
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#define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf
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#define EXYNOS_PIN_FUNC_INPUT 0
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#define EXYNOS_PIN_FUNC_OUTPUT 1
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#define EXYNOS_PIN_FUNC_2 2
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#define EXYNOS_PIN_FUNC_3 3
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#define EXYNOS_PIN_FUNC_4 4
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#define EXYNOS_PIN_FUNC_5 5
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#define EXYNOS_PIN_FUNC_6 6
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#define EXYNOS_PIN_FUNC_F 0xf
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#endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */
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