0b741b8234
This commit adds support for the Broadcom STB S2/S3/S5 suspend states on ARM based SoCs. This requires quite a lot of code in order to deal with the different HW blocks that need to be quiesced during suspend: - DDR PHY SHIM - DDR memory controller and sequencer - control processor The final steps of the suspend execute in an on-chip SRAM and there is a little bit of assembly code in order to shut down the DDR PHY PLL and then go into a wfi loop until a wake-up even occurs. Conversely the resume part involves waiting for the DDR PHY PLL to come back up and resume executions where we left. For S3, because of our memory hashing (actual hashing code not included for simplicity, and is bypassed) we need to relocate the writable variables (stack) into SRAM shortly before suspending in order to leave the DRAM untouched and create a reliable hash of its contents. This code has been contributed by Brian Norris initially and has been incrementally fixed and updated to support new chips by a lot of people. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Markus Mayer <mmayer@broadcom.com> Signed-off-by: Justin Chen <justinpopo6@gmail.com> Signed-off-by: Gareth Powell <gpowell@broadcom.com> Signed-off-by: Doug Berger <opendmb@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
77 lines
1.7 KiB
ArmAsm
77 lines
1.7 KiB
ArmAsm
/*
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* Copyright © 2014-2017 Broadcom
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include "pm.h"
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.text
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.align 3
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#define AON_CTRL_REG r10
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#define DDR_PHY_STATUS_REG r11
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/*
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* r0: AON_CTRL base address
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* r1: DDRY PHY PLL status register address
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*/
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ENTRY(brcmstb_pm_do_s2)
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stmfd sp!, {r4-r11, lr}
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mov AON_CTRL_REG, r0
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mov DDR_PHY_STATUS_REG, r1
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/* Flush memory transactions */
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dsb
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/* Cache DDR_PHY_STATUS_REG translation */
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ldr r0, [DDR_PHY_STATUS_REG]
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/* power down request */
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ldr r0, =PM_S2_COMMAND
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ldr r1, =0
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str r1, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
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ldr r1, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
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str r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
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ldr r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
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/* Wait for interrupt */
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wfi
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nop
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/* Bring MEMC back up */
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1: ldr r0, [DDR_PHY_STATUS_REG]
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ands r0, #1
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beq 1b
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/* Power-up handshake */
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ldr r0, =1
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str r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS]
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ldr r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS]
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ldr r0, =0
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str r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
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ldr r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
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/* Return to caller */
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ldr r0, =0
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ldmfd sp!, {r4-r11, pc}
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ENDPROC(brcmstb_pm_do_s2)
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/* Place literal pool here */
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.ltorg
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ENTRY(brcmstb_pm_do_s2_sz)
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.word . - brcmstb_pm_do_s2
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