360fe725f8
After commit e509bd7da1 ("genirq: Allow migration of chained
interrupts by installing default action") Loongson-3 fails at here:
setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction);
This is because both chained_action and cascade_irqaction don't have
IRQF_SHARED flag. This will cause Loongson-3 resume fails because HPET
timer interrupt can't be delivered during S3. So we set the irqchip of
the chained irq to loongson_irq_chip which doesn't disable the chained
irq in CP0.Status.
Cc: stable@vger.kernel.org
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20434/
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Huacai Chen <chenhuacai@gmail.com>
45 lines
1.6 KiB
C
45 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_MACH_LOONGSON64_IRQ_H_
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#define __ASM_MACH_LOONGSON64_IRQ_H_
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#include <boot_param.h>
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#ifdef CONFIG_CPU_LOONGSON3
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/* cpu core interrupt numbers */
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#define MIPS_CPU_IRQ_BASE 56
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#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */
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#define LOONGSON_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 3) /* CASCADE */
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#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */
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#define LOONGSON_HT1_CFG_BASE loongson_sysconf.ht_control_base
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#define LOONGSON_HT1_INT_VECTOR_BASE (LOONGSON_HT1_CFG_BASE + 0x80)
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#define LOONGSON_HT1_INT_EN_BASE (LOONGSON_HT1_CFG_BASE + 0xa0)
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#define LOONGSON_HT1_INT_VECTOR(n) \
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LOONGSON3_REG32(LOONGSON_HT1_INT_VECTOR_BASE, 4 * (n))
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#define LOONGSON_HT1_INTN_EN(n) \
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LOONGSON3_REG32(LOONGSON_HT1_INT_EN_BASE, 4 * (n))
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#define LOONGSON_INT_ROUTER_OFFSET 0x1400
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#define LOONGSON_INT_ROUTER_INTEN \
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LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x24)
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#define LOONGSON_INT_ROUTER_INTENSET \
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LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x28)
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#define LOONGSON_INT_ROUTER_INTENCLR \
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LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x2c)
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#define LOONGSON_INT_ROUTER_ENTRY(n) \
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LOONGSON3_REG8(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + n)
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#define LOONGSON_INT_ROUTER_LPC LOONGSON_INT_ROUTER_ENTRY(0x0a)
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#define LOONGSON_INT_ROUTER_HT1(n) LOONGSON_INT_ROUTER_ENTRY(n + 0x18)
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#define LOONGSON_INT_COREx_INTy(x, y) (1<<(x) | 1<<(y+4)) /* route to int y of core x */
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#endif
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extern void fixup_irqs(void);
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extern void loongson3_ipi_interrupt(struct pt_regs *regs);
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#include_next <irq.h>
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#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */
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