forked from Minki/linux
ddcbabf440
Kill the remaining shift macro in favor of calculating at compile time its value from the more descriptive mask, which gives us a better representation of the register layout. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
958 lines
22 KiB
C
958 lines
22 KiB
C
/*
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* Marvell 88E6xxx Switch Port Registers support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2016-2017 Savoir-faire Linux Inc.
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* Vivien Didelot <vivien.didelot@savoirfairelinux.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/bitfield.h>
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#include <linux/if_bridge.h>
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#include <linux/phy.h>
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#include "chip.h"
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#include "port.h"
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int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
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u16 *val)
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{
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int addr = chip->info->port_base_addr + port;
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return mv88e6xxx_read(chip, addr, reg, val);
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}
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int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
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u16 val)
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{
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int addr = chip->info->port_base_addr + port;
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return mv88e6xxx_write(chip, addr, reg, val);
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}
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/* Offset 0x01: MAC (or PCS or Physical) Control Register
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*
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* Link, Duplex and Flow Control have one force bit, one value bit.
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*
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* For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
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* Alternative values require the 200BASE (or AltSpeed) bit 12 set.
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* Newer chips need a ForcedSpd bit 13 set to consider the value.
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*/
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static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
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phy_interface_t mode)
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{
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u16 reg;
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int err;
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err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
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if (err)
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return err;
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reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
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MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK);
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switch (mode) {
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case PHY_INTERFACE_MODE_RGMII_RXID:
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reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK;
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break;
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case PHY_INTERFACE_MODE_RGMII_TXID:
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reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
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break;
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case PHY_INTERFACE_MODE_RGMII_ID:
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reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
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MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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break;
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default:
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return 0;
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}
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err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
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if (err)
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return err;
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dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port,
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reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no",
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reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no");
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return 0;
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}
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int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
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phy_interface_t mode)
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{
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if (port < 5)
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return -EOPNOTSUPP;
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return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
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}
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int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
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phy_interface_t mode)
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{
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if (port != 0)
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return -EOPNOTSUPP;
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return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
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}
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int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
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{
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u16 reg;
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int err;
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err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
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if (err)
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return err;
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reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
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MV88E6XXX_PORT_MAC_CTL_LINK_UP);
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switch (link) {
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case LINK_FORCED_DOWN:
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reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK;
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break;
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case LINK_FORCED_UP:
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reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
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MV88E6XXX_PORT_MAC_CTL_LINK_UP;
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break;
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case LINK_UNFORCED:
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/* normal link detection */
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break;
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default:
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return -EINVAL;
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}
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err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
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if (err)
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return err;
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dev_dbg(chip->dev, "p%d: %s link %s\n", port,
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reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce",
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reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down");
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return 0;
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}
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int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup)
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{
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u16 reg;
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int err;
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err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
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if (err)
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return err;
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reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
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MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL);
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switch (dup) {
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case DUPLEX_HALF:
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reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX;
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break;
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case DUPLEX_FULL:
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reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
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MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL;
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break;
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case DUPLEX_UNFORCED:
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/* normal duplex detection */
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break;
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default:
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return -EINVAL;
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}
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err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
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if (err)
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return err;
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dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
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reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
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reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
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return 0;
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}
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static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip *chip, int port,
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int speed, bool alt_bit, bool force_bit)
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{
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u16 reg, ctrl;
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int err;
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switch (speed) {
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case 10:
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ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10;
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break;
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case 100:
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ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100;
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break;
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case 200:
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if (alt_bit)
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ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 |
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MV88E6390_PORT_MAC_CTL_ALTSPEED;
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else
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ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200;
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break;
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case 1000:
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ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
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break;
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case 2500:
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ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
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MV88E6390_PORT_MAC_CTL_ALTSPEED;
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break;
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case 10000:
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/* all bits set, fall through... */
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case SPEED_UNFORCED:
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ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED;
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break;
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default:
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return -EOPNOTSUPP;
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}
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err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
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if (err)
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return err;
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reg &= ~MV88E6XXX_PORT_MAC_CTL_SPEED_MASK;
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if (alt_bit)
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reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED;
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if (force_bit) {
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reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
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if (speed != SPEED_UNFORCED)
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ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
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}
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reg |= ctrl;
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err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
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if (err)
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return err;
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if (speed)
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dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
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else
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dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
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return 0;
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}
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/* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */
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int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
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{
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if (speed == SPEED_MAX)
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speed = 200;
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if (speed > 200)
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return -EOPNOTSUPP;
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/* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */
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return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
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}
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/* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
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int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
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{
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if (speed == SPEED_MAX)
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speed = 1000;
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if (speed == 200 || speed > 1000)
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return -EOPNOTSUPP;
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return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
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}
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/* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
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int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
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{
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if (speed == SPEED_MAX)
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speed = 1000;
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if (speed > 1000)
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return -EOPNOTSUPP;
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if (speed == 200 && port < 5)
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return -EOPNOTSUPP;
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return mv88e6xxx_port_set_speed(chip, port, speed, true, false);
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}
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/* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
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int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
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{
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if (speed == SPEED_MAX)
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speed = port < 9 ? 1000 : 2500;
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if (speed > 2500)
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return -EOPNOTSUPP;
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if (speed == 200 && port != 0)
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return -EOPNOTSUPP;
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if (speed == 2500 && port < 9)
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return -EOPNOTSUPP;
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return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
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}
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/* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
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int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
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{
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if (speed == SPEED_MAX)
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speed = port < 9 ? 1000 : 10000;
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if (speed == 200 && port != 0)
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return -EOPNOTSUPP;
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if (speed >= 2500 && port < 9)
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return -EOPNOTSUPP;
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return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
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}
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int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
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phy_interface_t mode)
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{
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u16 reg;
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u16 cmode;
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int err;
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if (mode == PHY_INTERFACE_MODE_NA)
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return 0;
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if (port != 9 && port != 10)
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return -EOPNOTSUPP;
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switch (mode) {
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case PHY_INTERFACE_MODE_1000BASEX:
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cmode = MV88E6XXX_PORT_STS_CMODE_1000BASE_X;
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break;
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case PHY_INTERFACE_MODE_SGMII:
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cmode = MV88E6XXX_PORT_STS_CMODE_SGMII;
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break;
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case PHY_INTERFACE_MODE_2500BASEX:
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cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX;
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break;
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case PHY_INTERFACE_MODE_XGMII:
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cmode = MV88E6XXX_PORT_STS_CMODE_XAUI;
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break;
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case PHY_INTERFACE_MODE_RXAUI:
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cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI;
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break;
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default:
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cmode = 0;
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}
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if (cmode) {
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err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
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if (err)
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return err;
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reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK;
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reg |= cmode;
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err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
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if (err)
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return err;
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}
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return 0;
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}
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int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
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{
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int err;
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u16 reg;
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err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
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if (err)
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return err;
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*cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK;
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return 0;
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}
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/* Offset 0x02: Jamming Control
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*
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* Do not limit the period of time that this port can be paused for by
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* the remote end or the period of time that this port can pause the
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* remote end.
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*/
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int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
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u8 out)
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{
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return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL,
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out << 8 | in);
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}
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int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
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u8 out)
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{
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int err;
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err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
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MV88E6390_PORT_FLOW_CTL_UPDATE |
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MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in);
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if (err)
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return err;
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return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
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MV88E6390_PORT_FLOW_CTL_UPDATE |
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MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out);
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}
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/* Offset 0x04: Port Control Register */
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static const char * const mv88e6xxx_port_state_names[] = {
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[MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled",
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[MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening",
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[MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning",
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[MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding",
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};
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int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
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{
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u16 reg;
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int err;
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err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
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if (err)
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return err;
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reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK;
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switch (state) {
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case BR_STATE_DISABLED:
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state = MV88E6XXX_PORT_CTL0_STATE_DISABLED;
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break;
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case BR_STATE_BLOCKING:
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case BR_STATE_LISTENING:
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state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
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break;
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case BR_STATE_LEARNING:
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state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
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break;
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case BR_STATE_FORWARDING:
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state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
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break;
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default:
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return -EINVAL;
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}
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reg |= state;
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err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
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if (err)
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return err;
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dev_dbg(chip->dev, "p%d: PortState set to %s\n", port,
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mv88e6xxx_port_state_names[state]);
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return 0;
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}
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int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
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enum mv88e6xxx_egress_mode mode)
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{
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int err;
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u16 reg;
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err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
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if (err)
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return err;
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reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK;
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switch (mode) {
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case MV88E6XXX_EGRESS_MODE_UNMODIFIED:
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reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED;
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break;
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case MV88E6XXX_EGRESS_MODE_UNTAGGED:
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reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED;
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break;
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case MV88E6XXX_EGRESS_MODE_TAGGED:
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reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED;
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break;
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case MV88E6XXX_EGRESS_MODE_ETHERTYPE:
|
|
reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
|
|
}
|
|
|
|
int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
|
|
enum mv88e6xxx_frame_mode mode)
|
|
{
|
|
int err;
|
|
u16 reg;
|
|
|
|
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
|
|
|
|
switch (mode) {
|
|
case MV88E6XXX_FRAME_MODE_NORMAL:
|
|
reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
|
|
break;
|
|
case MV88E6XXX_FRAME_MODE_DSA:
|
|
reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
|
|
}
|
|
|
|
int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
|
|
enum mv88e6xxx_frame_mode mode)
|
|
{
|
|
int err;
|
|
u16 reg;
|
|
|
|
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
|
|
|
|
switch (mode) {
|
|
case MV88E6XXX_FRAME_MODE_NORMAL:
|
|
reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
|
|
break;
|
|
case MV88E6XXX_FRAME_MODE_DSA:
|
|
reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
|
|
break;
|
|
case MV88E6XXX_FRAME_MODE_PROVIDER:
|
|
reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER;
|
|
break;
|
|
case MV88E6XXX_FRAME_MODE_ETHERTYPE:
|
|
reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
|
|
}
|
|
|
|
static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
|
|
int port, bool unicast)
|
|
{
|
|
int err;
|
|
u16 reg;
|
|
|
|
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
if (unicast)
|
|
reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
|
|
else
|
|
reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
|
|
|
|
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
|
|
}
|
|
|
|
int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
|
|
bool unicast, bool multicast)
|
|
{
|
|
int err;
|
|
u16 reg;
|
|
|
|
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK;
|
|
|
|
if (unicast && multicast)
|
|
reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA;
|
|
else if (unicast)
|
|
reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA;
|
|
else if (multicast)
|
|
reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA;
|
|
else
|
|
reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA;
|
|
|
|
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
|
|
}
|
|
|
|
/* Offset 0x05: Port Control 1 */
|
|
|
|
int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
|
|
bool message_port)
|
|
{
|
|
u16 val;
|
|
int err;
|
|
|
|
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
|
|
if (err)
|
|
return err;
|
|
|
|
if (message_port)
|
|
val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
|
|
else
|
|
val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
|
|
|
|
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
|
|
}
|
|
|
|
/* Offset 0x06: Port Based VLAN Map */
|
|
|
|
int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
|
|
{
|
|
const u16 mask = mv88e6xxx_port_mask(chip);
|
|
u16 reg;
|
|
int err;
|
|
|
|
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
reg &= ~mask;
|
|
reg |= map & mask;
|
|
|
|
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
|
|
if (err)
|
|
return err;
|
|
|
|
dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
|
|
{
|
|
const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
|
|
u16 reg;
|
|
int err;
|
|
|
|
/* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
|
|
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
*fid = (reg & 0xf000) >> 12;
|
|
|
|
/* Port's default FID upper bits are located in reg 0x05, offset 0 */
|
|
if (upper_mask) {
|
|
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
|
|
®);
|
|
if (err)
|
|
return err;
|
|
|
|
*fid |= (reg & upper_mask) << 4;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
|
|
{
|
|
const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
|
|
u16 reg;
|
|
int err;
|
|
|
|
if (fid >= mv88e6xxx_num_databases(chip))
|
|
return -EINVAL;
|
|
|
|
/* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
|
|
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
reg &= 0x0fff;
|
|
reg |= (fid & 0x000f) << 12;
|
|
|
|
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Port's default FID upper bits are located in reg 0x05, offset 0 */
|
|
if (upper_mask) {
|
|
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
|
|
®);
|
|
if (err)
|
|
return err;
|
|
|
|
reg &= ~upper_mask;
|
|
reg |= (fid >> 4) & upper_mask;
|
|
|
|
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1,
|
|
reg);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Offset 0x07: Default Port VLAN ID & Priority */
|
|
|
|
int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
|
|
{
|
|
u16 reg;
|
|
int err;
|
|
|
|
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
|
|
®);
|
|
if (err)
|
|
return err;
|
|
|
|
*pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
|
|
{
|
|
u16 reg;
|
|
int err;
|
|
|
|
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
|
|
®);
|
|
if (err)
|
|
return err;
|
|
|
|
reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
|
|
reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
|
|
|
|
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
|
|
reg);
|
|
if (err)
|
|
return err;
|
|
|
|
dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Offset 0x08: Port Control 2 Register */
|
|
|
|
static const char * const mv88e6xxx_port_8021q_mode_names[] = {
|
|
[MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled",
|
|
[MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback",
|
|
[MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check",
|
|
[MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure",
|
|
};
|
|
|
|
static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
|
|
int port, bool multicast)
|
|
{
|
|
int err;
|
|
u16 reg;
|
|
|
|
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
if (multicast)
|
|
reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
|
|
else
|
|
reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
|
|
|
|
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
|
|
}
|
|
|
|
int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
|
|
bool unicast, bool multicast)
|
|
{
|
|
int err;
|
|
|
|
err = mv88e6185_port_set_forward_unknown(chip, port, unicast);
|
|
if (err)
|
|
return err;
|
|
|
|
return mv88e6185_port_set_default_forward(chip, port, multicast);
|
|
}
|
|
|
|
int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
|
|
int upstream_port)
|
|
{
|
|
int err;
|
|
u16 reg;
|
|
|
|
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK;
|
|
reg |= upstream_port;
|
|
|
|
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
|
|
}
|
|
|
|
int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
|
|
u16 mode)
|
|
{
|
|
u16 reg;
|
|
int err;
|
|
|
|
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
|
|
reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
|
|
|
|
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
|
|
if (err)
|
|
return err;
|
|
|
|
dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port,
|
|
mv88e6xxx_port_8021q_mode_names[mode]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port)
|
|
{
|
|
u16 reg;
|
|
int err;
|
|
|
|
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
reg |= MV88E6XXX_PORT_CTL2_MAP_DA;
|
|
|
|
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
|
|
}
|
|
|
|
int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
|
|
size_t size)
|
|
{
|
|
u16 reg;
|
|
int err;
|
|
|
|
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK;
|
|
|
|
if (size <= 1522)
|
|
reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522;
|
|
else if (size <= 2048)
|
|
reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048;
|
|
else if (size <= 10240)
|
|
reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240;
|
|
else
|
|
return -ERANGE;
|
|
|
|
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
|
|
}
|
|
|
|
/* Offset 0x09: Port Rate Control */
|
|
|
|
int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
|
|
{
|
|
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
|
|
0x0000);
|
|
}
|
|
|
|
int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
|
|
{
|
|
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
|
|
0x0001);
|
|
}
|
|
|
|
/* Offset 0x0C: Port ATU Control */
|
|
|
|
int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port)
|
|
{
|
|
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0);
|
|
}
|
|
|
|
/* Offset 0x0D: (Priority) Override Register */
|
|
|
|
int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
|
|
{
|
|
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0);
|
|
}
|
|
|
|
/* Offset 0x0f: Port Ether type */
|
|
|
|
int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
|
|
u16 etype)
|
|
{
|
|
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype);
|
|
}
|
|
|
|
/* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
|
|
* Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
|
|
*/
|
|
|
|
int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
|
|
{
|
|
int err;
|
|
|
|
/* Use a direct priority mapping for all IEEE tagged frames */
|
|
err = mv88e6xxx_port_write(chip, port,
|
|
MV88E6095_PORT_IEEE_PRIO_REMAP_0123,
|
|
0x3210);
|
|
if (err)
|
|
return err;
|
|
|
|
return mv88e6xxx_port_write(chip, port,
|
|
MV88E6095_PORT_IEEE_PRIO_REMAP_4567,
|
|
0x7654);
|
|
}
|
|
|
|
static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
|
|
int port, u16 table, u8 ptr, u16 data)
|
|
{
|
|
u16 reg;
|
|
|
|
reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table |
|
|
(ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) |
|
|
(data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK);
|
|
|
|
return mv88e6xxx_port_write(chip, port,
|
|
MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg);
|
|
}
|
|
|
|
int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
|
|
{
|
|
int err, i;
|
|
u16 table;
|
|
|
|
for (i = 0; i <= 7; i++) {
|
|
table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP;
|
|
err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i,
|
|
(i | i << 4));
|
|
if (err)
|
|
return err;
|
|
|
|
table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP;
|
|
err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
|
|
if (err)
|
|
return err;
|
|
|
|
table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP;
|
|
err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
|
|
if (err)
|
|
return err;
|
|
|
|
table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP;
|
|
err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|