a056ddce9b
Problems with current settings: 1. The min value was overrided to 0 on Vega20 & Navi10. While the expected should be -273.15 C. 2. The thermal min/max threshold was output in wrong unit on Navi10 & Arcturus. As TEMP_RANGE_MIN/MAX is already in millicelsius. And "*1000" in smu_v11_0_start_thermal_control makes the output wrongly. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
136 lines
3.9 KiB
C
136 lines
3.9 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __SMU_V11_0_H__
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#define __SMU_V11_0_H__
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#include "amdgpu_smu.h"
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#define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
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#define SMU11_DRIVER_IF_VERSION_VG20 0x13
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#define SMU11_DRIVER_IF_VERSION_ARCT 0x09
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#define SMU11_DRIVER_IF_VERSION_NV10 0x33
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#define SMU11_DRIVER_IF_VERSION_NV14 0x34
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/* MP Apertures */
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#define MP0_Public 0x03800000
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#define MP0_SRAM 0x03900000
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#define MP1_Public 0x03b00000
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#define MP1_SRAM 0x03c00004
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#define MP1_SMC_SIZE 0x40000
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/* address block */
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#define smnMP1_FIRMWARE_FLAGS 0x3010024
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#define smnMP0_FW_INTF 0x30101c0
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#define smnMP1_PUB_CTRL 0x3010b14
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#define TEMP_RANGE_MIN (0)
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#define TEMP_RANGE_MAX (80 * 1000)
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#define SMU11_TOOL_SIZE 0x19000
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#define CLK_MAP(clk, index) \
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[SMU_##clk] = {1, (index)}
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#define FEA_MAP(fea) \
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[SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}
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#define TAB_MAP(tab) \
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[SMU_TABLE_##tab] = {1, TABLE_##tab}
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#define PWR_MAP(tab) \
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[SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}
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#define WORKLOAD_MAP(profile, workload) \
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[profile] = {1, (workload)}
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static const struct smu_temperature_range smu11_thermal_policy[] =
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{
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{-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
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{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
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};
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struct smu_11_0_cmn2aisc_mapping {
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int valid_mapping;
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int map_to;
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};
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struct smu_11_0_max_sustainable_clocks {
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uint32_t display_clock;
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uint32_t phy_clock;
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uint32_t pixel_clock;
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uint32_t uclock;
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uint32_t dcef_clock;
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uint32_t soc_clock;
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};
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struct smu_11_0_dpm_table {
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uint32_t min; /* MHz */
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uint32_t max; /* MHz */
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};
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struct smu_11_0_dpm_tables {
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struct smu_11_0_dpm_table soc_table;
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struct smu_11_0_dpm_table gfx_table;
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struct smu_11_0_dpm_table uclk_table;
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struct smu_11_0_dpm_table eclk_table;
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struct smu_11_0_dpm_table vclk_table;
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struct smu_11_0_dpm_table dclk_table;
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struct smu_11_0_dpm_table dcef_table;
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struct smu_11_0_dpm_table pixel_table;
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struct smu_11_0_dpm_table display_table;
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struct smu_11_0_dpm_table phy_table;
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struct smu_11_0_dpm_table fclk_table;
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};
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struct smu_11_0_dpm_context {
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struct smu_11_0_dpm_tables dpm_tables;
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uint32_t workload_policy_mask;
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uint32_t dcef_min_ds_clk;
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};
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enum smu_11_0_power_state {
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SMU_11_0_POWER_STATE__D0 = 0,
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SMU_11_0_POWER_STATE__D1,
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SMU_11_0_POWER_STATE__D3, /* Sleep*/
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SMU_11_0_POWER_STATE__D4, /* Hibernate*/
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SMU_11_0_POWER_STATE__D5, /* Power off*/
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};
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struct smu_11_0_power_context {
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uint32_t power_source;
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uint8_t in_power_limit_boost_mode;
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enum smu_11_0_power_state power_state;
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};
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enum smu_v11_0_baco_seq {
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BACO_SEQ_BACO = 0,
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BACO_SEQ_MSR,
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BACO_SEQ_BAMACO,
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BACO_SEQ_ULPS,
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BACO_SEQ_COUNT,
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};
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void smu_v11_0_set_smu_funcs(struct smu_context *smu);
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#endif
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