41173abc57
Based on 1 normalized pattern(s): this program is free software you can distribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 32 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528170026.531157061@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
140 lines
5.0 KiB
C
140 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Defines for the MSP interrupt controller.
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*
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* Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
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* Author: Carsten Langgaard, carstenl@mips.com
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*
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* ########################################################################
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*
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* ########################################################################
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*/
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#ifndef _MSP_CIC_INT_H
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#define _MSP_CIC_INT_H
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/*
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* The PMC-Sierra CIC interrupts are all centrally managed by the
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* CIC sub-system.
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* We attempt to keep the interrupt numbers as consistent as possible
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* across all of the MSP devices, but some differences will creep in ...
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* The interrupts which are directly forwarded to the MIPS core interrupts
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* are assigned interrupts in the range 0-7, interrupts cascaded through
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* the CIC are assigned interrupts 8-39. The cascade occurs on C_IRQ4
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* (MSP_INT_CIC). Currently we don't really distinguish between VPE1
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* and VPE0 (or thread contexts for that matter). Will have to fix.
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* The PER interrupts are assigned interrupts in the range 40-71.
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*/
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/*
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* IRQs directly forwarded to the CPU
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*/
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#define MSP_MIPS_INTBASE 0
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#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */
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#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */
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#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */
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#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */
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#define MSP_INT_USB 4 /* IRQ for USB, C_IRQ2 */
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#define MSP_INT_SAR 5 /* IRQ for ADSL2+ SAR, C_IRQ3 */
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#define MSP_INT_CIC 6 /* IRQ for CIC block, C_IRQ4 */
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#define MSP_INT_SEC 7 /* IRQ for Sec engine, C_IRQ5 */
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/*
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* IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
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* These defines should be tied to the register definitions for the CIC
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* interrupt routine. For now, just use hard-coded values.
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*/
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#define MSP_CIC_INTBASE (MSP_MIPS_INTBASE + 8)
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#define MSP_INT_EXT0 (MSP_CIC_INTBASE + 0)
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/* External interrupt 0 */
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#define MSP_INT_EXT1 (MSP_CIC_INTBASE + 1)
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/* External interrupt 1 */
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#define MSP_INT_EXT2 (MSP_CIC_INTBASE + 2)
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/* External interrupt 2 */
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#define MSP_INT_EXT3 (MSP_CIC_INTBASE + 3)
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/* External interrupt 3 */
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#define MSP_INT_CPUIF (MSP_CIC_INTBASE + 4)
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/* CPU interface interrupt */
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#define MSP_INT_EXT4 (MSP_CIC_INTBASE + 5)
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/* External interrupt 4 */
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#define MSP_INT_CIC_USB (MSP_CIC_INTBASE + 6)
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/* Cascaded IRQ for USB */
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#define MSP_INT_MBOX (MSP_CIC_INTBASE + 7)
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/* Sec engine mailbox IRQ */
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#define MSP_INT_EXT5 (MSP_CIC_INTBASE + 8)
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/* External interrupt 5 */
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#define MSP_INT_TDM (MSP_CIC_INTBASE + 9)
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/* TDM interrupt */
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#define MSP_INT_CIC_MAC0 (MSP_CIC_INTBASE + 10)
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/* Cascaded IRQ for MAC 0 */
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#define MSP_INT_CIC_MAC1 (MSP_CIC_INTBASE + 11)
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/* Cascaded IRQ for MAC 1 */
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#define MSP_INT_CIC_SEC (MSP_CIC_INTBASE + 12)
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/* Cascaded IRQ for sec engine */
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#define MSP_INT_PER (MSP_CIC_INTBASE + 13)
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/* Peripheral interrupt */
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#define MSP_INT_TIMER0 (MSP_CIC_INTBASE + 14)
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/* SLP timer 0 */
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#define MSP_INT_TIMER1 (MSP_CIC_INTBASE + 15)
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/* SLP timer 1 */
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#define MSP_INT_TIMER2 (MSP_CIC_INTBASE + 16)
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/* SLP timer 2 */
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#define MSP_INT_VPE0_TIMER (MSP_CIC_INTBASE + 17)
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/* VPE0 MIPS timer */
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#define MSP_INT_BLKCP (MSP_CIC_INTBASE + 18)
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/* Block Copy */
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#define MSP_INT_UART0 (MSP_CIC_INTBASE + 19)
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/* UART 0 */
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#define MSP_INT_PCI (MSP_CIC_INTBASE + 20)
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/* PCI subsystem */
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#define MSP_INT_EXT6 (MSP_CIC_INTBASE + 21)
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/* External interrupt 5 */
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#define MSP_INT_PCI_MSI (MSP_CIC_INTBASE + 22)
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/* PCI Message Signal */
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#define MSP_INT_CIC_SAR (MSP_CIC_INTBASE + 23)
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/* Cascaded ADSL2+ SAR IRQ */
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#define MSP_INT_DSL (MSP_CIC_INTBASE + 24)
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/* ADSL2+ IRQ */
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#define MSP_INT_CIC_ERR (MSP_CIC_INTBASE + 25)
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/* SLP error condition */
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#define MSP_INT_VPE1_TIMER (MSP_CIC_INTBASE + 26)
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/* VPE1 MIPS timer */
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#define MSP_INT_VPE0_PC (MSP_CIC_INTBASE + 27)
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/* VPE0 Performance counter */
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#define MSP_INT_VPE1_PC (MSP_CIC_INTBASE + 28)
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/* VPE1 Performance counter */
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#define MSP_INT_EXT7 (MSP_CIC_INTBASE + 29)
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/* External interrupt 5 */
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#define MSP_INT_VPE0_SW (MSP_CIC_INTBASE + 30)
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/* VPE0 Software interrupt */
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#define MSP_INT_VPE1_SW (MSP_CIC_INTBASE + 31)
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/* VPE0 Software interrupt */
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/*
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* IRQs cascaded on CIC PER interrupt (MSP_INT_PER)
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*/
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#define MSP_PER_INTBASE (MSP_CIC_INTBASE + 32)
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/* Reserved 0-1 */
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#define MSP_INT_UART1 (MSP_PER_INTBASE + 2)
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/* UART 1 */
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/* Reserved 3-5 */
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#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6)
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/* 2-wire */
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#define MSP_INT_TM0 (MSP_PER_INTBASE + 7)
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/* Peripheral timer block out 0 */
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#define MSP_INT_TM1 (MSP_PER_INTBASE + 8)
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/* Peripheral timer block out 1 */
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/* Reserved 9 */
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#define MSP_INT_SPRX (MSP_PER_INTBASE + 10)
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/* SPI RX complete */
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#define MSP_INT_SPTX (MSP_PER_INTBASE + 11)
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/* SPI TX complete */
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#define MSP_INT_GPIO (MSP_PER_INTBASE + 12)
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/* GPIO */
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#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)
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/* Peripheral error */
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/* Reserved 14-31 */
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#endif /* !_MSP_CIC_INT_H */
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