forked from Minki/linux
9d218a1fcf
When the guest runs with caches disabled (like in an early boot sequence, for example), all the writes are diectly going to RAM, bypassing the caches altogether. Once the MMU and caches are enabled, whatever sits in the cache becomes suddenly visible, which isn't what the guest expects. A way to avoid this potential disaster is to invalidate the cache when the MMU is being turned on. For this, we hook into the SCTLR_EL1 trapping code, and scan the stage-2 page tables, invalidating the pages/sections that have already been mapped in. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
157 lines
4.6 KiB
C
157 lines
4.6 KiB
C
/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ARM64_KVM_MMU_H__
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#define __ARM64_KVM_MMU_H__
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#include <asm/page.h>
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#include <asm/memory.h>
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/*
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* As we only have the TTBR0_EL2 register, we cannot express
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* "negative" addresses. This makes it impossible to directly share
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* mappings with the kernel.
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*
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* Instead, give the HYP mode its own VA region at a fixed offset from
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* the kernel by just masking the top bits (which are all ones for a
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* kernel address).
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*/
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#define HYP_PAGE_OFFSET_SHIFT VA_BITS
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#define HYP_PAGE_OFFSET_MASK ((UL(1) << HYP_PAGE_OFFSET_SHIFT) - 1)
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#define HYP_PAGE_OFFSET (PAGE_OFFSET & HYP_PAGE_OFFSET_MASK)
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/*
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* Our virtual mapping for the idmap-ed MMU-enable code. Must be
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* shared across all the page-tables. Conveniently, we use the last
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* possible page, where no kernel mapping will ever exist.
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*/
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#define TRAMPOLINE_VA (HYP_PAGE_OFFSET_MASK & PAGE_MASK)
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#ifdef __ASSEMBLY__
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/*
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* Convert a kernel VA into a HYP VA.
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* reg: VA to be converted.
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*/
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.macro kern_hyp_va reg
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and \reg, \reg, #HYP_PAGE_OFFSET_MASK
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.endm
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#else
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#include <asm/cachetype.h>
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#include <asm/cacheflush.h>
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#define KERN_TO_HYP(kva) ((unsigned long)kva - PAGE_OFFSET + HYP_PAGE_OFFSET)
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/*
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* Align KVM with the kernel's view of physical memory. Should be
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* 40bit IPA, with PGD being 8kB aligned in the 4KB page configuration.
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*/
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#define KVM_PHYS_SHIFT PHYS_MASK_SHIFT
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#define KVM_PHYS_SIZE (1UL << KVM_PHYS_SHIFT)
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#define KVM_PHYS_MASK (KVM_PHYS_SIZE - 1UL)
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/* Make sure we get the right size, and thus the right alignment */
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#define PTRS_PER_S2_PGD (1 << (KVM_PHYS_SHIFT - PGDIR_SHIFT))
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#define S2_PGD_ORDER get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
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int create_hyp_mappings(void *from, void *to);
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int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
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void free_boot_hyp_pgd(void);
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void free_hyp_pgds(void);
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int kvm_alloc_stage2_pgd(struct kvm *kvm);
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void kvm_free_stage2_pgd(struct kvm *kvm);
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int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
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phys_addr_t pa, unsigned long size);
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int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
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void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
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phys_addr_t kvm_mmu_get_httbr(void);
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phys_addr_t kvm_mmu_get_boot_httbr(void);
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phys_addr_t kvm_get_idmap_vector(void);
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int kvm_mmu_init(void);
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void kvm_clear_hyp_idmap(void);
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#define kvm_set_pte(ptep, pte) set_pte(ptep, pte)
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#define kvm_set_pmd(pmdp, pmd) set_pmd(pmdp, pmd)
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static inline bool kvm_is_write_fault(unsigned long esr)
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{
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unsigned long esr_ec = esr >> ESR_EL2_EC_SHIFT;
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if (esr_ec == ESR_EL2_EC_IABT)
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return false;
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if ((esr & ESR_EL2_ISV) && !(esr & ESR_EL2_WNR))
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return false;
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return true;
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}
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static inline void kvm_clean_pgd(pgd_t *pgd) {}
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static inline void kvm_clean_pmd_entry(pmd_t *pmd) {}
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static inline void kvm_clean_pte(pte_t *pte) {}
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static inline void kvm_clean_pte_entry(pte_t *pte) {}
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static inline void kvm_set_s2pte_writable(pte_t *pte)
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{
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pte_val(*pte) |= PTE_S2_RDWR;
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}
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static inline void kvm_set_s2pmd_writable(pmd_t *pmd)
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{
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pmd_val(*pmd) |= PMD_S2_RDWR;
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}
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#define kvm_pgd_addr_end(addr, end) pgd_addr_end(addr, end)
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#define kvm_pud_addr_end(addr, end) pud_addr_end(addr, end)
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#define kvm_pmd_addr_end(addr, end) pmd_addr_end(addr, end)
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struct kvm;
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#define kvm_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
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static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
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{
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return (vcpu_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101;
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}
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static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,
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unsigned long size)
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{
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if (!vcpu_has_cache_enabled(vcpu))
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kvm_flush_dcache_to_poc((void *)hva, size);
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if (!icache_is_aliasing()) { /* PIPT */
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flush_icache_range(hva, hva + size);
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} else if (!icache_is_aivivt()) { /* non ASID-tagged VIVT */
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/* any kind of VIPT cache */
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__flush_icache_all();
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}
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}
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#define kvm_virt_to_phys(x) __virt_to_phys((unsigned long)(x))
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void stage2_flush_vm(struct kvm *kvm);
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#endif /* __ASSEMBLY__ */
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#endif /* __ARM64_KVM_MMU_H__ */
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