forked from Minki/linux
cde214a890
Platform data and resources for core devices are kmemdup()ed when the corresponding devices are registered and can thus be declared as const. Do so. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
291 lines
8.1 KiB
C
291 lines
8.1 KiB
C
/*
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* r8a7790 processor support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/clocksource.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/of_platform.h>
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#include <linux/platform_data/gpio-rcar.h>
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#include <linux/platform_data/irq-renesas-irqc.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_timer.h>
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#include <mach/common.h>
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#include <mach/irqs.h>
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#include <mach/r8a7790.h>
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#include <asm/mach/arch.h>
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static const struct resource pfc_resources[] __initconst = {
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DEFINE_RES_MEM(0xe6060000, 0x250),
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};
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#define R8A7790_GPIO(idx) \
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static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \
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DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \
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DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
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}; \
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\
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static const struct gpio_rcar_config \
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r8a7790_gpio##idx##_platform_data __initconst = { \
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.gpio_base = 32 * (idx), \
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.irq_base = 0, \
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.number_of_pins = 32, \
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.pctl_name = "pfc-r8a7790", \
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.has_both_edge_trigger = 1, \
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}; \
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R8A7790_GPIO(0);
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R8A7790_GPIO(1);
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R8A7790_GPIO(2);
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R8A7790_GPIO(3);
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R8A7790_GPIO(4);
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R8A7790_GPIO(5);
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#define r8a7790_register_gpio(idx) \
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platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
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r8a7790_gpio##idx##_resources, \
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ARRAY_SIZE(r8a7790_gpio##idx##_resources), \
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&r8a7790_gpio##idx##_platform_data, \
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sizeof(r8a7790_gpio##idx##_platform_data))
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void __init r8a7790_pinmux_init(void)
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{
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platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
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ARRAY_SIZE(pfc_resources));
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r8a7790_register_gpio(0);
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r8a7790_register_gpio(1);
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r8a7790_register_gpio(2);
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r8a7790_register_gpio(3);
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r8a7790_register_gpio(4);
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r8a7790_register_gpio(5);
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}
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#define SCIF_COMMON(scif_type, baseaddr, irq) \
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.type = scif_type, \
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.mapbase = baseaddr, \
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
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.irqs = SCIx_IRQ_MUXED(irq)
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#define SCIFA_DATA(index, baseaddr, irq) \
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[index] = { \
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SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
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.scbrr_algo_id = SCBRR_ALGO_4, \
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
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}
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#define SCIFB_DATA(index, baseaddr, irq) \
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[index] = { \
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SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
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.scbrr_algo_id = SCBRR_ALGO_4, \
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.scscr = SCSCR_RE | SCSCR_TE, \
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}
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#define SCIF_DATA(index, baseaddr, irq) \
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[index] = { \
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SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
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.scbrr_algo_id = SCBRR_ALGO_2, \
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.scscr = SCSCR_RE | SCSCR_TE, \
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}
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#define HSCIF_DATA(index, baseaddr, irq) \
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[index] = { \
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SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
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.scbrr_algo_id = SCBRR_ALGO_6, \
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.scscr = SCSCR_RE | SCSCR_TE, \
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}
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enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
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HSCIF0, HSCIF1 };
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static const struct plat_sci_port scif[] __initconst = {
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SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
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SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
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SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
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SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
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SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
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SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
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SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
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SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
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HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */
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HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */
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};
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static inline void r8a7790_register_scif(int idx)
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{
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platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
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sizeof(struct plat_sci_port));
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}
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static const struct renesas_irqc_config irqc0_data __initconst = {
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.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
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};
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static const struct resource irqc0_resources[] __initconst = {
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DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
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DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
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DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
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DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
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DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
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};
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#define r8a7790_register_irqc(idx) \
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platform_device_register_resndata(&platform_bus, "renesas_irqc", \
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idx, irqc##idx##_resources, \
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ARRAY_SIZE(irqc##idx##_resources), \
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&irqc##idx##_data, \
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sizeof(struct renesas_irqc_config))
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static const struct resource thermal_resources[] __initconst = {
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DEFINE_RES_MEM(0xe61f0000, 0x14),
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DEFINE_RES_MEM(0xe61f0100, 0x38),
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DEFINE_RES_IRQ(gic_spi(69)),
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};
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#define r8a7790_register_thermal() \
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platform_device_register_simple("rcar_thermal", -1, \
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thermal_resources, \
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ARRAY_SIZE(thermal_resources))
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static const struct sh_timer_config cmt00_platform_data __initconst = {
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.name = "CMT00",
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.timer_bit = 0,
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.clockevent_rating = 80,
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};
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static const struct resource cmt00_resources[] __initconst = {
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DEFINE_RES_MEM(0xffca0510, 0x0c),
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DEFINE_RES_MEM(0xffca0500, 0x04),
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DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
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};
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#define r8a7790_register_cmt(idx) \
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platform_device_register_resndata(&platform_bus, "sh_cmt", \
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idx, cmt##idx##_resources, \
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ARRAY_SIZE(cmt##idx##_resources), \
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&cmt##idx##_platform_data, \
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sizeof(struct sh_timer_config))
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void __init r8a7790_add_dt_devices(void)
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{
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r8a7790_register_scif(SCIFA0);
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r8a7790_register_scif(SCIFA1);
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r8a7790_register_scif(SCIFB0);
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r8a7790_register_scif(SCIFB1);
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r8a7790_register_scif(SCIFB2);
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r8a7790_register_scif(SCIFA2);
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r8a7790_register_scif(SCIF0);
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r8a7790_register_scif(SCIF1);
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r8a7790_register_scif(HSCIF0);
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r8a7790_register_scif(HSCIF1);
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r8a7790_register_cmt(00);
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}
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void __init r8a7790_add_standard_devices(void)
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{
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r8a7790_add_dt_devices();
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r8a7790_register_irqc(0);
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r8a7790_register_thermal();
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}
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#define MODEMR 0xe6160060
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u32 __init r8a7790_read_mode_pins(void)
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{
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void __iomem *modemr = ioremap_nocache(MODEMR, 4);
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u32 mode;
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BUG_ON(!modemr);
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mode = ioread32(modemr);
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iounmap(modemr);
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return mode;
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}
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#define CNTCR 0
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#define CNTFID0 0x20
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void __init r8a7790_timer_init(void)
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{
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#ifdef CONFIG_ARM_ARCH_TIMER
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u32 mode = r8a7790_read_mode_pins();
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void __iomem *base;
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int extal_mhz = 0;
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u32 freq;
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/* At Linux boot time the r8a7790 arch timer comes up
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* with the counter disabled. Moreover, it may also report
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* a potentially incorrect fixed 13 MHz frequency. To be
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* correct these registers need to be updated to use the
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* frequency EXTAL / 2 which can be determined by the MD pins.
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*/
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switch (mode & (MD(14) | MD(13))) {
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case 0:
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extal_mhz = 15;
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break;
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case MD(13):
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extal_mhz = 20;
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break;
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case MD(14):
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extal_mhz = 26;
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break;
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case MD(13) | MD(14):
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extal_mhz = 30;
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break;
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}
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/* The arch timer frequency equals EXTAL / 2 */
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freq = extal_mhz * (1000000 / 2);
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/* Remap "armgcnt address map" space */
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base = ioremap(0xe6080000, PAGE_SIZE);
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/* Update registers with correct frequency */
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iowrite32(freq, base + CNTFID0);
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asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
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/* make sure arch timer is started by setting bit 0 of CNTCR */
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iowrite32(1, base + CNTCR);
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iounmap(base);
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#endif /* CONFIG_ARM_ARCH_TIMER */
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clocksource_of_init();
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}
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void __init r8a7790_init_early(void)
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{
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#ifndef CONFIG_ARM_ARCH_TIMER
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shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
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#endif
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}
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#ifdef CONFIG_USE_OF
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static const char * const r8a7790_boards_compat_dt[] __initconst = {
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"renesas,r8a7790",
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NULL,
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};
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DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
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.init_early = r8a7790_init_early,
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.init_time = r8a7790_timer_init,
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.dt_compat = r8a7790_boards_compat_dt,
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MACHINE_END
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#endif /* CONFIG_USE_OF */
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