forked from Minki/linux
30b842889e
This adds support for the spear13xx platform, which has first been under review a long time ago and finally been completed after generic spear work has gone into the clock, dt and pinctrl branches. Also a number of updates for the samsung socs are part of this branch. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJPuezDAAoJEIwa5zzehBx3mooP/iTHd1wRjr2MzKNx4+LpLWgl aAXH002xe9Lvu7m75BRvEYWWdRLkyEy9ARM4s2wJCnxU41KmbF65ED1erxK8xaSe Ako34vzH+HiUCM2DLzIP6FXyJMM7OcfrdGaY/GxOv+U+MzGUHeu3Q+8b0B/yfBnm M3HdDrpyZHKZP9UM3wVQ4/ilDck6vEjYSV2jC11IaHiDMRD2nSpfRKh8H3+gv65S gtj9EZpWM8CZg/fCe5lsm3PZnBnqHHW3WVafVnDQfGWeJYqZxMB5QKLU6qf/ntpx LU2WjXoGaMmGBVZWynrwNEY6GVp3fZrDV30/q8Htf0/fBpEjUncrLHXtw0DxkpnK UuyoRgn7zxOc3kDzohFNIexp1K3q+PNzXklR9hg7OSVji+9bPd2LIOEnpBeghBGj WzZIebz5dIdddHlnOl4fRdmxZva2UTuI4bFAJ0izi10Mup7A9lrENnFHG/iVA0rQ QlqJZoyeDCvbXQqZCgHirYRPhIxXdQj4G5IivfRxQ7Jgjy76Kt9uDp1egwezF/3a 2jVtcK42XokVv3Dhsvq9UNFn9GWdVImZ7eh70XLv+q834zAVxSzjWLtlS8I1Q5WO 7BGIJaICtugNwgYr44Dif6nsoVUmMnSwU5hVw1pApKZspN6EhMhMdp2hw8JPHFUs mrZdHi1NAWuYSbObc3UB =W2Ri -----END PGP SIGNATURE----- Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull arm-soc: soc specific changes (part 2) from Olof Johansson: "This adds support for the spear13xx platform, which has first been under review a long time ago and finally been completed after generic spear work has gone into the clock, dt and pinctrl branches. Also a number of updates for the samsung socs are part of this branch." Fix up trivial conflicts in drivers/gpio/gpio-samsung.c that look much worse than they are: the exonys5 init code was refactored in commitfd454997d6("gpio: samsung: refactor gpiolib init for exynos4/5"), and then commitf10590c983("ARM: EXYNOS: add GPC4 bank instance") added a new gpio chip define and did tiny updates to the init code. So the conflict diff looks like hell, but it's actually a fairly simple change. * tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (34 commits) ARM: exynos: fix building with CONFIG_OF disabled ARM: EXYNOS: Add AUXDATA for i2c controllers ARM: dts: Update device tree source files for EXYNOS5250 ARM: EXYNOS: Add device tree support for interrupt combiner ARM: EXYNOS: Add irq_domain support for interrupt combiner ARM: EXYNOS: Remove a new bus_type instance for EXYNOS5 ARM: EXYNOS: update irqs for EXYNOS5250 SoC ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll ARM: EXYNOS: add GPC4 bank instance ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition ARM: EXYNOS: Modify the GIC physical address for static io-mapping ARM: EXYNOS: Add watchdog timer clock instance pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res SPEAr: Update MAINTAINERS and Documentation SPEAr13xx: Add defconfig SPEAr13xx: Add compilation support SPEAr13xx: Add dts and dtsi files pinctrl: Add SPEAr13xx pinctrl drivers pinctrl: SPEAr: Create macro for declaring GPIO PINS SPEAr13xx: Add common clock framework support ...
276 lines
8.6 KiB
C
276 lines
8.6 KiB
C
/* linux/arch/arm/mach-exynos/include/mach/map.h
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* EXYNOS4 - Memory map definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_MAP_H
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#define __ASM_ARCH_MAP_H __FILE__
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#include <plat/map-base.h>
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/*
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* EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
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* So need to define it, and here is to avoid redefinition warning.
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*/
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#define S3C_UART_OFFSET (0x10000)
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#include <plat/map-s5p.h>
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#define EXYNOS4_PA_SYSRAM0 0x02025000
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#define EXYNOS4_PA_SYSRAM1 0x02020000
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#define EXYNOS5_PA_SYSRAM 0x02020000
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#define EXYNOS4_PA_FIMC0 0x11800000
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#define EXYNOS4_PA_FIMC1 0x11810000
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#define EXYNOS4_PA_FIMC2 0x11820000
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#define EXYNOS4_PA_FIMC3 0x11830000
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#define EXYNOS4_PA_JPEG 0x11840000
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/* x = 0...1 */
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#define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000))
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#define EXYNOS4_PA_G2D 0x12800000
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#define EXYNOS4_PA_I2S0 0x03830000
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#define EXYNOS4_PA_I2S1 0xE3100000
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#define EXYNOS4_PA_I2S2 0xE2A00000
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#define EXYNOS4_PA_PCM0 0x03840000
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#define EXYNOS4_PA_PCM1 0x13980000
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#define EXYNOS4_PA_PCM2 0x13990000
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#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
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#define EXYNOS4_PA_ONENAND 0x0C000000
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#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
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#define EXYNOS_PA_CHIPID 0x10000000
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#define EXYNOS4_PA_SYSCON 0x10010000
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#define EXYNOS5_PA_SYSCON 0x10050100
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#define EXYNOS4_PA_PMU 0x10020000
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#define EXYNOS5_PA_PMU 0x10040000
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#define EXYNOS4_PA_CMU 0x10030000
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#define EXYNOS5_PA_CMU 0x10010000
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#define EXYNOS4_PA_SYSTIMER 0x10050000
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#define EXYNOS5_PA_SYSTIMER 0x101C0000
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#define EXYNOS4_PA_WATCHDOG 0x10060000
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#define EXYNOS5_PA_WATCHDOG 0x101D0000
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#define EXYNOS4_PA_RTC 0x10070000
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#define EXYNOS4_PA_KEYPAD 0x100A0000
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#define EXYNOS4_PA_DMC0 0x10400000
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#define EXYNOS4_PA_DMC1 0x10410000
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#define EXYNOS4_PA_COMBINER 0x10440000
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#define EXYNOS5_PA_COMBINER 0x10440000
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#define EXYNOS4_PA_GIC_CPU 0x10480000
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#define EXYNOS4_PA_GIC_DIST 0x10490000
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#define EXYNOS5_PA_GIC_CPU 0x10482000
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#define EXYNOS5_PA_GIC_DIST 0x10481000
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#define EXYNOS4_PA_COREPERI 0x10500000
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#define EXYNOS4_PA_TWD 0x10500600
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#define EXYNOS4_PA_L2CC 0x10502000
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#define EXYNOS4_PA_MDMA0 0x10810000
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#define EXYNOS4_PA_MDMA1 0x12840000
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#define EXYNOS4_PA_PDMA0 0x12680000
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#define EXYNOS4_PA_PDMA1 0x12690000
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#define EXYNOS5_PA_MDMA0 0x10800000
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#define EXYNOS5_PA_MDMA1 0x11C10000
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#define EXYNOS5_PA_PDMA0 0x121A0000
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#define EXYNOS5_PA_PDMA1 0x121B0000
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#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
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#define EXYNOS4_PA_SYSMMU_2D_ACP 0x10A40000
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#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
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#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
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#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
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#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
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#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
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#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
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#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
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#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
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#define EXYNOS4_PA_SYSMMU_FIMC_ISP 0x12260000
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#define EXYNOS4_PA_SYSMMU_FIMC_DRC 0x12270000
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#define EXYNOS4_PA_SYSMMU_FIMC_FD 0x122A0000
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#define EXYNOS4_PA_SYSMMU_ISPCPU 0x122B0000
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#define EXYNOS4_PA_SYSMMU_FIMC_LITE0 0x123B0000
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#define EXYNOS4_PA_SYSMMU_FIMC_LITE1 0x123C0000
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#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
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#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
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#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
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#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
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#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
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#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
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#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
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#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000
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#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000
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#define EXYNOS5_PA_SYSMMU_2D 0x10A60000
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#define EXYNOS5_PA_SYSMMU_MFC_L 0x11200000
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#define EXYNOS5_PA_SYSMMU_MFC_R 0x11210000
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#define EXYNOS5_PA_SYSMMU_ROTATOR 0x11D40000
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#define EXYNOS5_PA_SYSMMU_MDMA2 0x11D50000
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#define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000
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#define EXYNOS5_PA_SYSMMU_IOP 0x12360000
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#define EXYNOS5_PA_SYSMMU_RTIC 0x12370000
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#define EXYNOS5_PA_SYSMMU_GPS 0x12630000
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#define EXYNOS5_PA_SYSMMU_ISP 0x13260000
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#define EXYNOS5_PA_SYSMMU_DRC 0x12370000
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#define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000
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#define EXYNOS5_PA_SYSMMU_SCALERP 0x13290000
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#define EXYNOS5_PA_SYSMMU_FD 0x132A0000
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#define EXYNOS5_PA_SYSMMU_ISPCPU 0x132B0000
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#define EXYNOS5_PA_SYSMMU_ODC 0x132C0000
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#define EXYNOS5_PA_SYSMMU_DIS0 0x132D0000
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#define EXYNOS5_PA_SYSMMU_DIS1 0x132E0000
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#define EXYNOS5_PA_SYSMMU_3DNR 0x132F0000
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#define EXYNOS5_PA_SYSMMU_LITE0 0x13C40000
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#define EXYNOS5_PA_SYSMMU_LITE1 0x13C50000
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#define EXYNOS5_PA_SYSMMU_GSC0 0x13E80000
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#define EXYNOS5_PA_SYSMMU_GSC1 0x13E90000
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#define EXYNOS5_PA_SYSMMU_GSC2 0x13EA0000
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#define EXYNOS5_PA_SYSMMU_GSC3 0x13EB0000
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#define EXYNOS5_PA_SYSMMU_FIMD1 0x14640000
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#define EXYNOS5_PA_SYSMMU_TV 0x14650000
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#define EXYNOS4_PA_SPI0 0x13920000
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#define EXYNOS4_PA_SPI1 0x13930000
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#define EXYNOS4_PA_SPI2 0x13940000
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#define EXYNOS4_PA_GPIO1 0x11400000
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#define EXYNOS4_PA_GPIO2 0x11000000
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#define EXYNOS4_PA_GPIO3 0x03860000
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#define EXYNOS5_PA_GPIO1 0x11400000
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#define EXYNOS5_PA_GPIO2 0x13400000
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#define EXYNOS5_PA_GPIO3 0x10D10000
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#define EXYNOS5_PA_GPIO4 0x03860000
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#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
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#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
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#define EXYNOS4_PA_FIMD0 0x11C00000
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#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
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#define EXYNOS4_PA_DWMCI 0x12550000
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#define EXYNOS4_PA_HSOTG 0x12480000
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#define EXYNOS4_PA_USB_HSPHY 0x125B0000
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#define EXYNOS4_PA_SATA 0x12560000
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#define EXYNOS4_PA_SATAPHY 0x125D0000
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#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
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#define EXYNOS4_PA_SROMC 0x12570000
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#define EXYNOS5_PA_SROMC 0x12250000
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#define EXYNOS4_PA_EHCI 0x12580000
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#define EXYNOS4_PA_OHCI 0x12590000
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#define EXYNOS4_PA_HSPHY 0x125B0000
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#define EXYNOS4_PA_MFC 0x13400000
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#define EXYNOS4_PA_UART 0x13800000
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#define EXYNOS5_PA_UART 0x12C00000
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#define EXYNOS4_PA_VP 0x12C00000
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#define EXYNOS4_PA_MIXER 0x12C10000
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#define EXYNOS4_PA_SDO 0x12C20000
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#define EXYNOS4_PA_HDMI 0x12D00000
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#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
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#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
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#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000))
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#define EXYNOS4_PA_ADC 0x13910000
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#define EXYNOS4_PA_ADC1 0x13911000
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#define EXYNOS4_PA_AC97 0x139A0000
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#define EXYNOS4_PA_SPDIF 0x139B0000
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#define EXYNOS4_PA_TIMER 0x139D0000
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#define EXYNOS5_PA_TIMER 0x12DD0000
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#define EXYNOS4_PA_SDRAM 0x40000000
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#define EXYNOS5_PA_SDRAM 0x40000000
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/* Compatibiltiy Defines */
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#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
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#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
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#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
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#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
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#define S3C_PA_IIC EXYNOS4_PA_IIC(0)
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#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
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#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
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#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
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#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
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#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
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#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
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#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
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#define S3C_PA_RTC EXYNOS4_PA_RTC
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#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
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#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
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#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
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#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
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#define S3C_PA_USB_HSOTG EXYNOS4_PA_HSOTG
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#define S5P_PA_EHCI EXYNOS4_PA_EHCI
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#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
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#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
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#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
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#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
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#define S5P_PA_JPEG EXYNOS4_PA_JPEG
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#define S5P_PA_G2D EXYNOS4_PA_G2D
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#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
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#define S5P_PA_HDMI EXYNOS4_PA_HDMI
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#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
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#define S5P_PA_MFC EXYNOS4_PA_MFC
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#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
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#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
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#define S5P_PA_MIXER EXYNOS4_PA_MIXER
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#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
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#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
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#define S5P_PA_SDO EXYNOS4_PA_SDO
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#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
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#define S5P_PA_VP EXYNOS4_PA_VP
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#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
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#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
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#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
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/* Compatibility UART */
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#define EXYNOS4_PA_UART0 0x13800000
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#define EXYNOS4_PA_UART1 0x13810000
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#define EXYNOS4_PA_UART2 0x13820000
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#define EXYNOS4_PA_UART3 0x13830000
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#define EXYNOS4_SZ_UART SZ_256
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#define EXYNOS5_PA_UART0 0x12C00000
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#define EXYNOS5_PA_UART1 0x12C10000
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#define EXYNOS5_PA_UART2 0x12C20000
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#define EXYNOS5_PA_UART3 0x12C30000
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#define EXYNOS5_SZ_UART SZ_256
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#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
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#endif /* __ASM_ARCH_MAP_H */
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