forked from Minki/linux
9eaaf2076d
The current driver had a hardcoded minimum value of 2 for pixel clock divisor (PCD). This doesn't seem to be right. OMAP4 TRM says that PCD can be 1 when not downscaling, and inverted pixel clock (IPC) is off. OMAP3 TRM says the same, but also in the register descriptions that PCD value 1 is invalid. OMAP2 TRM says PCD 2 is the minimum. OMAP2 is still untested, but for both OMAP3 and OMAP4 PCD of 1 seems to work fine. This patch adds a new DSS feature, FEAT_PARAM_DSS_PCD, which is used to find the minimum and maximum PCD. The minimum is set to 2 for OMAP2, and 1 for OMAP3/4. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
111 lines
3.4 KiB
C
111 lines
3.4 KiB
C
/*
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* linux/drivers/video/omap2/dss/dss_features.h
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*
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* Copyright (C) 2010 Texas Instruments
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* Author: Archit Taneja <archit@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __OMAP2_DSS_FEATURES_H
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#define __OMAP2_DSS_FEATURES_H
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#if defined(CONFIG_OMAP4_DSS_HDMI)
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#include "ti_hdmi.h"
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#endif
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#define MAX_DSS_MANAGERS 3
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#define MAX_DSS_OVERLAYS 3
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#define MAX_DSS_LCD_MANAGERS 2
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#define MAX_NUM_DSI 2
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/* DSS has feature id */
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enum dss_feat_id {
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FEAT_GLOBAL_ALPHA = 1 << 0,
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FEAT_LCDENABLEPOL = 1 << 3,
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FEAT_LCDENABLESIGNAL = 1 << 4,
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FEAT_PCKFREEENABLE = 1 << 5,
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FEAT_FUNCGATED = 1 << 6,
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FEAT_MGR_LCD2 = 1 << 7,
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FEAT_LINEBUFFERSPLIT = 1 << 8,
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FEAT_ROWREPEATENABLE = 1 << 9,
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FEAT_RESIZECONF = 1 << 10,
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/* Independent core clk divider */
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FEAT_CORE_CLK_DIV = 1 << 11,
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FEAT_LCD_CLK_SRC = 1 << 12,
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/* DSI-PLL power command 0x3 is not working */
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FEAT_DSI_PLL_PWR_BUG = 1 << 13,
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FEAT_DSI_PLL_FREQSEL = 1 << 14,
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FEAT_DSI_DCS_CMD_CONFIG_VC = 1 << 15,
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FEAT_DSI_VC_OCP_WIDTH = 1 << 16,
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FEAT_DSI_REVERSE_TXCLKESC = 1 << 17,
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FEAT_DSI_GNQ = 1 << 18,
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FEAT_HDMI_CTS_SWMODE = 1 << 19,
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FEAT_HANDLE_UV_SEPARATE = 1 << 20,
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FEAT_ATTR2 = 1 << 21,
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FEAT_VENC_REQUIRES_TV_DAC_CLK = 1 << 22,
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FEAT_CPR = 1 << 23,
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FEAT_PRELOAD = 1 << 24,
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FEAT_FIR_COEF_V = 1 << 25,
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};
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/* DSS register field id */
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enum dss_feat_reg_field {
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FEAT_REG_FIRHINC,
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FEAT_REG_FIRVINC,
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FEAT_REG_FIFOHIGHTHRESHOLD,
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FEAT_REG_FIFOLOWTHRESHOLD,
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FEAT_REG_FIFOSIZE,
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FEAT_REG_HORIZONTALACCU,
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FEAT_REG_VERTICALACCU,
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FEAT_REG_DISPC_CLK_SWITCH,
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FEAT_REG_DSIPLL_REGN,
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FEAT_REG_DSIPLL_REGM,
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FEAT_REG_DSIPLL_REGM_DISPC,
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FEAT_REG_DSIPLL_REGM_DSI,
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};
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enum dss_range_param {
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FEAT_PARAM_DSS_FCK,
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FEAT_PARAM_DSS_PCD,
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FEAT_PARAM_DSIPLL_REGN,
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FEAT_PARAM_DSIPLL_REGM,
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FEAT_PARAM_DSIPLL_REGM_DISPC,
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FEAT_PARAM_DSIPLL_REGM_DSI,
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FEAT_PARAM_DSIPLL_FINT,
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FEAT_PARAM_DSIPLL_LPDIV,
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};
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/* DSS Feature Functions */
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int dss_feat_get_num_mgrs(void);
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int dss_feat_get_num_ovls(void);
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unsigned long dss_feat_get_param_min(enum dss_range_param param);
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unsigned long dss_feat_get_param_max(enum dss_range_param param);
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enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
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enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
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enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane);
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bool dss_feat_color_mode_supported(enum omap_plane plane,
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enum omap_color_mode color_mode);
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const char *dss_feat_get_clk_source_name(enum omap_dss_clk_source id);
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u32 dss_feat_get_buffer_size_unit(void); /* in bytes */
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u32 dss_feat_get_burst_size_unit(void); /* in bytes */
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bool dss_has_feature(enum dss_feat_id id);
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void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end);
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void dss_features_init(void);
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#if defined(CONFIG_OMAP4_DSS_HDMI)
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void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data);
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#endif
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#endif
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