forked from Minki/linux
33a732f407
This fetches the required firmware image from the filesystem,
then loads it into the GuC's memory via a dedicated DMA engine.
This patch is derived from GuC loading work originally done by
Vinit Azad and Ben Widawsky.
v2:
Various improvements per review comments by Chris Wilson
v3:
Removed 'wait' parameter to intel_guc_ucode_load() as firmware
prefetch is no longer supported in the common firmware loader,
per Daniel Vetter's request.
Firmware checker callback fn now returns errno rather than bool.
v4:
Squash uC-independent code into GuC-specifc loader [Daniel Vetter]
Don't keep the driver working (by falling back to execlist mode)
if GuC firmware loading fails [Daniel Vetter]
v5:
Clarify WOPCM-related #defines [Tom O'Rourke]
Delete obsolete code no longer required with current h/w & f/w
[Tom O'Rourke]
Move the call to intel_guc_ucode_init() later, so that it can
allocate GEM objects, and have it fetch the firmware; then
intel_guc_ucode_load() doesn't need to fetch it later.
[Daniel Vetter].
v6:
Update comment describing intel_guc_ucode_load() [Tom O'Rourke]
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
108 lines
3.8 KiB
C
108 lines
3.8 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef _I915_GUC_REG_H_
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#define _I915_GUC_REG_H_
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/* Definitions of GuC H/W registers, bits, etc */
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#define GUC_STATUS 0xc000
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#define GS_BOOTROM_SHIFT 1
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#define GS_BOOTROM_MASK (0x7F << GS_BOOTROM_SHIFT)
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#define GS_BOOTROM_RSA_FAILED (0x50 << GS_BOOTROM_SHIFT)
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#define GS_UKERNEL_SHIFT 8
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#define GS_UKERNEL_MASK (0xFF << GS_UKERNEL_SHIFT)
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#define GS_UKERNEL_LAPIC_DONE (0x30 << GS_UKERNEL_SHIFT)
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#define GS_UKERNEL_DPC_ERROR (0x60 << GS_UKERNEL_SHIFT)
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#define GS_UKERNEL_READY (0xF0 << GS_UKERNEL_SHIFT)
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#define GS_MIA_SHIFT 16
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#define GS_MIA_MASK (0x07 << GS_MIA_SHIFT)
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#define SOFT_SCRATCH(n) (0xc180 + ((n) * 4))
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#define UOS_RSA_SCRATCH_0 0xc200
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#define DMA_ADDR_0_LOW 0xc300
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#define DMA_ADDR_0_HIGH 0xc304
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#define DMA_ADDR_1_LOW 0xc308
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#define DMA_ADDR_1_HIGH 0xc30c
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#define DMA_ADDRESS_SPACE_WOPCM (7 << 16)
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#define DMA_ADDRESS_SPACE_GTT (8 << 16)
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#define DMA_COPY_SIZE 0xc310
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#define DMA_CTRL 0xc314
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#define UOS_MOVE (1<<4)
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#define START_DMA (1<<0)
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#define DMA_GUC_WOPCM_OFFSET 0xc340
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#define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */
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#define GUC_WOPCM_SIZE 0xc050
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#define GUC_WOPCM_SIZE_VALUE (0x80 << 12) /* 512KB */
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/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
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#define GUC_WOPCM_TOP (GUC_WOPCM_SIZE_VALUE)
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#define GEN8_GT_PM_CONFIG 0x138140
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#define GEN9LP_GT_PM_CONFIG 0x138140
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#define GEN9_GT_PM_CONFIG 0x13816c
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#define GT_DOORBELL_ENABLE (1<<0)
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#define GEN8_GTCR 0x4274
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#define GEN8_GTCR_INVALIDATE (1<<0)
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#define GUC_ARAT_C6DIS 0xA178
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#define GUC_SHIM_CONTROL 0xc064
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#define GUC_DISABLE_SRAM_INIT_TO_ZEROES (1<<0)
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#define GUC_ENABLE_READ_CACHE_LOGIC (1<<1)
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#define GUC_ENABLE_MIA_CACHING (1<<2)
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#define GUC_GEN10_MSGCH_ENABLE (1<<4)
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#define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA (1<<9)
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#define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA (1<<10)
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#define GUC_ENABLE_MIA_CLOCK_GATING (1<<15)
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#define GUC_GEN10_SHIM_WC_ENABLE (1<<21)
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#define GUC_SHIM_CONTROL_VALUE (GUC_DISABLE_SRAM_INIT_TO_ZEROES | \
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GUC_ENABLE_READ_CACHE_LOGIC | \
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GUC_ENABLE_MIA_CACHING | \
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GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | \
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GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | \
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GUC_ENABLE_MIA_CLOCK_GATING)
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#define HOST2GUC_INTERRUPT 0xc4c8
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#define HOST2GUC_TRIGGER (1<<0)
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#define DRBMISC1 0x1984
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#define DOORBELL_ENABLE (1<<0)
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#define GEN8_DRBREGL(x) (0x1000 + (x) * 8)
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#define GEN8_DRB_VALID (1<<0)
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#define GEN8_DRBREGU(x) (GEN8_DRBREGL(x) + 4)
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#define DE_GUCRMR 0x44054
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#define GUC_BCS_RCS_IER 0xC550
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#define GUC_VCS2_VCS1_IER 0xC554
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#define GUC_WD_VECS_IER 0xC558
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#define GUC_PM_P24C_IER 0xC55C
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#endif
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