forked from Minki/linux
4ac46db1aa
Support for the futex_atomic_* operations by using the load-link/store-conditional l.lwa/l.swa instructions. Most openrisc cores provide these instructions now if not available, emulation is provided. Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> [shorne@gmail.com: remove OPENRISC_HAVE_INST_LWA_SWA config suggesed by Alan Cox https://lkml.org/lkml/2014/7/23/666] Signed-off-by: Stafford Horne <shorne@gmail.com>
136 lines
2.9 KiB
C
136 lines
2.9 KiB
C
#ifndef __ASM_OPENRISC_FUTEX_H
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#define __ASM_OPENRISC_FUTEX_H
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#ifdef __KERNEL__
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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#include <asm/errno.h>
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#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
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({ \
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__asm__ __volatile__ ( \
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"1: l.lwa %0, %2 \n" \
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insn "\n" \
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"2: l.swa %2, %1 \n" \
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" l.bnf 1b \n" \
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" l.ori %1, r0, 0 \n" \
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"3: \n" \
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".section .fixup,\"ax\" \n" \
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"4: l.j 3b \n" \
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" l.addi %1, r0, %3 \n" \
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".previous \n" \
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".section __ex_table,\"a\" \n" \
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".word 1b,4b,2b,4b \n" \
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".previous \n" \
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: "=&r" (oldval), "=&r" (ret), "+m" (*uaddr) \
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: "i" (-EFAULT), "r" (oparg) \
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: "cc", "memory" \
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); \
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})
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static inline int
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futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
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{
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int op = (encoded_op >> 28) & 7;
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int cmp = (encoded_op >> 24) & 15;
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int oparg = (encoded_op << 8) >> 20;
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int cmparg = (encoded_op << 20) >> 20;
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int oldval = 0, ret;
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if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
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oparg = 1 << oparg;
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if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
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return -EFAULT;
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pagefault_disable();
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op("l.or %1,%4,%4", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op("l.add %1,%0,%4", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op("l.or %1,%0,%4", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op("l.and %1,%0,%4", ret, oldval, uaddr, ~oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op("l.xor %1,%0,%4", ret, oldval, uaddr, oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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pagefault_enable();
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if (!ret) {
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switch (cmp) {
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case FUTEX_OP_CMP_EQ:
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ret = (oldval == cmparg);
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break;
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case FUTEX_OP_CMP_NE:
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ret = (oldval != cmparg);
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break;
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case FUTEX_OP_CMP_LT:
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ret = (oldval < cmparg);
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break;
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case FUTEX_OP_CMP_GE:
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ret = (oldval >= cmparg);
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break;
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case FUTEX_OP_CMP_LE:
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ret = (oldval <= cmparg);
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break;
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case FUTEX_OP_CMP_GT:
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ret = (oldval > cmparg);
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break;
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default:
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ret = -ENOSYS;
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}
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}
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return ret;
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}
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static inline int
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futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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u32 oldval, u32 newval)
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{
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int ret = 0;
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u32 prev;
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if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
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return -EFAULT;
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__asm__ __volatile__ ( \
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"1: l.lwa %1, %2 \n" \
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" l.sfeq %1, %3 \n" \
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" l.bnf 3f \n" \
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" l.nop \n" \
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"2: l.swa %2, %4 \n" \
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" l.bnf 1b \n" \
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" l.nop \n" \
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"3: \n" \
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".section .fixup,\"ax\" \n" \
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"4: l.j 3b \n" \
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" l.addi %0, r0, %5 \n" \
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".previous \n" \
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".section __ex_table,\"a\" \n" \
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".word 1b,4b,2b,4b \n" \
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".previous \n" \
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: "+r" (ret), "=&r" (prev), "+m" (*uaddr) \
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: "r" (oldval), "r" (newval), "i" (-EFAULT) \
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: "cc", "memory" \
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);
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*uval = prev;
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return ret;
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}
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#endif /* __KERNEL__ */
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#endif /* __ASM_OPENRISC_FUTEX_H */
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