c13d1683df
Implement the fpsimd save restore, keeping the lazy part in assembler (as returning to C would be overkill). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
144 lines
3.9 KiB
C
144 lines
3.9 KiB
C
/*
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* Copyright (C) 2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hyp.h"
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static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)
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{
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u64 val;
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/*
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* We are about to set CPTR_EL2.TFP to trap all floating point
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* register accesses to EL2, however, the ARM ARM clearly states that
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* traps are only taken to EL2 if the operation would not otherwise
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* trap to EL1. Therefore, always make sure that for 32-bit guests,
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* we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
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*/
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val = vcpu->arch.hcr_el2;
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if (!(val & HCR_RW)) {
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write_sysreg(1 << 30, fpexc32_el2);
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isb();
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}
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write_sysreg(val, hcr_el2);
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/* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */
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write_sysreg(1 << 15, hstr_el2);
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write_sysreg(CPTR_EL2_TTA | CPTR_EL2_TFP, cptr_el2);
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write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
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}
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static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu)
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{
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write_sysreg(HCR_RW, hcr_el2);
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write_sysreg(0, hstr_el2);
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write_sysreg(read_sysreg(mdcr_el2) & MDCR_EL2_HPMN_MASK, mdcr_el2);
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write_sysreg(0, cptr_el2);
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}
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static void __hyp_text __activate_vm(struct kvm_vcpu *vcpu)
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{
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struct kvm *kvm = kern_hyp_va(vcpu->kvm);
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write_sysreg(kvm->arch.vttbr, vttbr_el2);
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}
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static void __hyp_text __deactivate_vm(struct kvm_vcpu *vcpu)
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{
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write_sysreg(0, vttbr_el2);
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}
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static hyp_alternate_select(__vgic_call_save_state,
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__vgic_v2_save_state, __vgic_v3_save_state,
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ARM64_HAS_SYSREG_GIC_CPUIF);
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static hyp_alternate_select(__vgic_call_restore_state,
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__vgic_v2_restore_state, __vgic_v3_restore_state,
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ARM64_HAS_SYSREG_GIC_CPUIF);
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static void __hyp_text __vgic_save_state(struct kvm_vcpu *vcpu)
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{
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__vgic_call_save_state()(vcpu);
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write_sysreg(read_sysreg(hcr_el2) & ~HCR_INT_OVERRIDE, hcr_el2);
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}
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static void __hyp_text __vgic_restore_state(struct kvm_vcpu *vcpu)
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{
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u64 val;
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val = read_sysreg(hcr_el2);
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val |= HCR_INT_OVERRIDE;
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val |= vcpu->arch.irq_lines;
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write_sysreg(val, hcr_el2);
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__vgic_call_restore_state()(vcpu);
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}
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int __hyp_text __guest_run(struct kvm_vcpu *vcpu)
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{
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struct kvm_cpu_context *host_ctxt;
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struct kvm_cpu_context *guest_ctxt;
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bool fp_enabled;
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u64 exit_code;
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vcpu = kern_hyp_va(vcpu);
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write_sysreg(vcpu, tpidr_el2);
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host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
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guest_ctxt = &vcpu->arch.ctxt;
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__sysreg_save_state(host_ctxt);
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__debug_cond_save_host_state(vcpu);
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__activate_traps(vcpu);
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__activate_vm(vcpu);
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__vgic_restore_state(vcpu);
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__timer_restore_state(vcpu);
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/*
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* We must restore the 32-bit state before the sysregs, thanks
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* to Cortex-A57 erratum #852523.
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*/
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__sysreg32_restore_state(vcpu);
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__sysreg_restore_state(guest_ctxt);
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__debug_restore_state(vcpu, kern_hyp_va(vcpu->arch.debug_ptr), guest_ctxt);
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/* Jump in the fire! */
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exit_code = __guest_enter(vcpu, host_ctxt);
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/* And we're baaack! */
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fp_enabled = __fpsimd_enabled();
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__sysreg_save_state(guest_ctxt);
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__sysreg32_save_state(vcpu);
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__timer_save_state(vcpu);
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__vgic_save_state(vcpu);
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__deactivate_traps(vcpu);
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__deactivate_vm(vcpu);
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__sysreg_restore_state(host_ctxt);
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if (fp_enabled) {
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__fpsimd_save_state(&guest_ctxt->gp_regs.fp_regs);
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__fpsimd_restore_state(&host_ctxt->gp_regs.fp_regs);
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}
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__debug_save_state(vcpu, kern_hyp_va(vcpu->arch.debug_ptr), guest_ctxt);
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__debug_cond_restore_host_state(vcpu);
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return exit_code;
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}
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