George Shen c11099b0d1 drm/amd/display: Add vendor specific LTTPR workarounds for DCN31 ... [Why] Certain LTTPR require special workarounds in order to comply with DP specifications. [How] Implement vendor specific sequences via DPCD writes to vendor-specific LTTPR registers. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: George Shen <George.Shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-12-01 16:06:25 -05:00
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acp
amdgpu	drm/amdgpu: Don't halt RLC on GFX suspend	2021-12-01 16:04:23 -05:00
amdkfd	drm/amdgpu: handle IH ring1 overflow	2021-12-01 16:03:34 -05:00
display	drm/amd/display: Add vendor specific LTTPR workarounds for DCN31	2021-12-01 16:06:25 -05:00
include	amdgpu/pm: Create shared array of power profile name strings	2021-12-01 16:03:42 -05:00
pm	drm/amdgpu: Don't halt RLC on GFX suspend	2021-12-01 16:04:23 -05:00