Ard Biesheuvel c0e50736e8 ARM: 9057/1: cache-v7: add missing ISB after cache level selection ...

A write to CSSELR needs to complete before its results can be observed
via CCSIDR. So add a ISB to ensure that this is the case.

Acked-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

2021-03-09 10:25:17 +00:00

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