Files
linux/arch/arm/mm
Ard Biesheuvel c0e50736e8 ARM: 9057/1: cache-v7: add missing ISB after cache level selection
A write to CSSELR needs to complete before its results can be observed
via CCSIDR. So add a ISB to ensure that this is the case.

Acked-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2021-03-09 10:25:17 +00:00
..
2019-09-24 15:54:08 -07:00
2021-01-15 17:42:10 +01:00
2019-11-11 17:19:40 +01:00