forked from Minki/linux
c0c0d996d0
This updates the powermac SMP code to use the mpic driver instead of the openpic driver and fixes the SMP-dependent context switch code. We had a subtle bug where we were using interrupt numbers 256-259 for IPIs, but ppc32 had NR_IRQS = 256. Moved the IPIs down to use interrupt numbers 252-255 instead. Signed-off-by: Paul Mackerras <paulus@samba.org>
717 lines
18 KiB
C
717 lines
18 KiB
C
/*
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* SMP support for power macintosh.
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*
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* We support both the old "powersurge" SMP architecture
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* and the current Core99 (G4 PowerMac) machines.
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*
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* Note that we don't support the very first rev. of
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* Apple/DayStar 2 CPUs board, the one with the funky
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* watchdog. Hopefully, none of these should be there except
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* maybe internally to Apple. I should probably still add some
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* code to detect this card though and disable SMP. --BenH.
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*
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* Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
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* and Ben Herrenschmidt <benh@kernel.crashing.org>.
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*
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* Support for DayStar quad CPU cards
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* Copyright (C) XLR8, Inc. 1994-2000
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/smp_lock.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <linux/hardirq.h>
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#include <linux/cpu.h>
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#include <asm/ptrace.h>
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#include <asm/atomic.h>
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#include <asm/irq.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/smp.h>
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#include <asm/residual.h>
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#include <asm/machdep.h>
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#include <asm/pmac_feature.h>
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#include <asm/time.h>
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#include <asm/mpic.h>
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#include <asm/cacheflush.h>
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#include <asm/keylargo.h>
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/*
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* Powersurge (old powermac SMP) support.
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*/
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extern void __secondary_start_pmac_0(void);
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/* Addresses for powersurge registers */
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#define HAMMERHEAD_BASE 0xf8000000
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#define HHEAD_CONFIG 0x90
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#define HHEAD_SEC_INTR 0xc0
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/* register for interrupting the primary processor on the powersurge */
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/* N.B. this is actually the ethernet ROM! */
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#define PSURGE_PRI_INTR 0xf3019000
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/* register for storing the start address for the secondary processor */
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/* N.B. this is the PCI config space address register for the 1st bridge */
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#define PSURGE_START 0xf2800000
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/* Daystar/XLR8 4-CPU card */
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#define PSURGE_QUAD_REG_ADDR 0xf8800000
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#define PSURGE_QUAD_IRQ_SET 0
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#define PSURGE_QUAD_IRQ_CLR 1
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#define PSURGE_QUAD_IRQ_PRIMARY 2
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#define PSURGE_QUAD_CKSTOP_CTL 3
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#define PSURGE_QUAD_PRIMARY_ARB 4
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#define PSURGE_QUAD_BOARD_ID 6
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#define PSURGE_QUAD_WHICH_CPU 7
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#define PSURGE_QUAD_CKSTOP_RDBK 8
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#define PSURGE_QUAD_RESET_CTL 11
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#define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v)))
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#define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
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#define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
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#define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
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/* virtual addresses for the above */
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static volatile u8 __iomem *hhead_base;
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static volatile u8 __iomem *quad_base;
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static volatile u32 __iomem *psurge_pri_intr;
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static volatile u8 __iomem *psurge_sec_intr;
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static volatile u32 __iomem *psurge_start;
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/* values for psurge_type */
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#define PSURGE_NONE -1
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#define PSURGE_DUAL 0
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#define PSURGE_QUAD_OKEE 1
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#define PSURGE_QUAD_COTTON 2
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#define PSURGE_QUAD_ICEGRASS 3
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/* what sort of powersurge board we have */
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static int psurge_type = PSURGE_NONE;
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/* L2 and L3 cache settings to pass from CPU0 to CPU1 */
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volatile static long int core99_l2_cache;
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volatile static long int core99_l3_cache;
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/* Timebase freeze GPIO */
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static unsigned int core99_tb_gpio;
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/* Sync flag for HW tb sync */
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static volatile int sec_tb_reset = 0;
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static unsigned int pri_tb_hi, pri_tb_lo;
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static unsigned int pri_tb_stamp;
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static void __devinit core99_init_caches(int cpu)
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{
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if (!cpu_has_feature(CPU_FTR_L2CR))
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return;
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if (cpu == 0) {
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core99_l2_cache = _get_L2CR();
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printk("CPU0: L2CR is %lx\n", core99_l2_cache);
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} else {
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printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
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_set_L2CR(0);
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_set_L2CR(core99_l2_cache);
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printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
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}
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if (!cpu_has_feature(CPU_FTR_L3CR))
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return;
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if (cpu == 0){
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core99_l3_cache = _get_L3CR();
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printk("CPU0: L3CR is %lx\n", core99_l3_cache);
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} else {
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printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
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_set_L3CR(0);
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_set_L3CR(core99_l3_cache);
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printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
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}
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}
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/*
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* Set and clear IPIs for powersurge.
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*/
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static inline void psurge_set_ipi(int cpu)
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{
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if (psurge_type == PSURGE_NONE)
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return;
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if (cpu == 0)
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in_be32(psurge_pri_intr);
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else if (psurge_type == PSURGE_DUAL)
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out_8(psurge_sec_intr, 0);
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else
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PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
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}
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static inline void psurge_clr_ipi(int cpu)
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{
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if (cpu > 0) {
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switch(psurge_type) {
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case PSURGE_DUAL:
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out_8(psurge_sec_intr, ~0);
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case PSURGE_NONE:
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break;
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default:
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PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
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}
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}
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}
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/*
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* On powersurge (old SMP powermac architecture) we don't have
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* separate IPIs for separate messages like openpic does. Instead
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* we have a bitmap for each processor, where a 1 bit means that
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* the corresponding message is pending for that processor.
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* Ideally each cpu's entry would be in a different cache line.
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* -- paulus.
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*/
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static unsigned long psurge_smp_message[NR_CPUS];
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void psurge_smp_message_recv(struct pt_regs *regs)
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{
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int cpu = smp_processor_id();
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int msg;
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/* clear interrupt */
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psurge_clr_ipi(cpu);
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if (num_online_cpus() < 2)
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return;
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/* make sure there is a message there */
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for (msg = 0; msg < 4; msg++)
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if (test_and_clear_bit(msg, &psurge_smp_message[cpu]))
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smp_message_recv(msg, regs);
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}
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irqreturn_t psurge_primary_intr(int irq, void *d, struct pt_regs *regs)
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{
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psurge_smp_message_recv(regs);
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return IRQ_HANDLED;
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}
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static void smp_psurge_message_pass(int target, int msg, unsigned long data,
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int wait)
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{
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int i;
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if (num_online_cpus() < 2)
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return;
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for (i = 0; i < NR_CPUS; i++) {
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if (!cpu_online(i))
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continue;
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if (target == MSG_ALL
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|| (target == MSG_ALL_BUT_SELF && i != smp_processor_id())
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|| target == i) {
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set_bit(msg, &psurge_smp_message[i]);
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psurge_set_ipi(i);
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}
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}
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}
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/*
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* Determine a quad card presence. We read the board ID register, we
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* force the data bus to change to something else, and we read it again.
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* It it's stable, then the register probably exist (ugh !)
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*/
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static int __init psurge_quad_probe(void)
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{
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int type;
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unsigned int i;
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type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
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if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
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|| type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
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return PSURGE_DUAL;
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/* looks OK, try a slightly more rigorous test */
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/* bogus is not necessarily cacheline-aligned,
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though I don't suppose that really matters. -- paulus */
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for (i = 0; i < 100; i++) {
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volatile u32 bogus[8];
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bogus[(0+i)%8] = 0x00000000;
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bogus[(1+i)%8] = 0x55555555;
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bogus[(2+i)%8] = 0xFFFFFFFF;
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bogus[(3+i)%8] = 0xAAAAAAAA;
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bogus[(4+i)%8] = 0x33333333;
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bogus[(5+i)%8] = 0xCCCCCCCC;
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bogus[(6+i)%8] = 0xCCCCCCCC;
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bogus[(7+i)%8] = 0x33333333;
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wmb();
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asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
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mb();
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if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
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return PSURGE_DUAL;
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}
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return type;
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}
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static void __init psurge_quad_init(void)
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{
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int procbits;
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if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
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procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
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if (psurge_type == PSURGE_QUAD_ICEGRASS)
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PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
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else
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PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
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mdelay(33);
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out_8(psurge_sec_intr, ~0);
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PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
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PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
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if (psurge_type != PSURGE_QUAD_ICEGRASS)
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PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
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PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
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mdelay(33);
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PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
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mdelay(33);
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PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
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mdelay(33);
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}
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static int __init smp_psurge_probe(void)
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{
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int i, ncpus;
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/* We don't do SMP on the PPC601 -- paulus */
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if (PVR_VER(mfspr(SPRN_PVR)) == 1)
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return 1;
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/*
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* The powersurge cpu board can be used in the generation
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* of powermacs that have a socket for an upgradeable cpu card,
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* including the 7500, 8500, 9500, 9600.
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* The device tree doesn't tell you if you have 2 cpus because
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* OF doesn't know anything about the 2nd processor.
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* Instead we look for magic bits in magic registers,
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* in the hammerhead memory controller in the case of the
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* dual-cpu powersurge board. -- paulus.
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*/
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if (find_devices("hammerhead") == NULL)
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return 1;
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hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
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quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
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psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
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psurge_type = psurge_quad_probe();
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if (psurge_type != PSURGE_DUAL) {
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psurge_quad_init();
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/* All released cards using this HW design have 4 CPUs */
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ncpus = 4;
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} else {
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iounmap(quad_base);
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if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
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/* not a dual-cpu card */
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iounmap(hhead_base);
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psurge_type = PSURGE_NONE;
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return 1;
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}
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ncpus = 2;
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}
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psurge_start = ioremap(PSURGE_START, 4);
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psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
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/* this is not actually strictly necessary -- paulus. */
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for (i = 1; i < ncpus; ++i)
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smp_hw_index[i] = i;
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if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
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return ncpus;
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}
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static void __init smp_psurge_kick_cpu(int nr)
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{
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unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
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unsigned long a;
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/* may need to flush here if secondary bats aren't setup */
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for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
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asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
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asm volatile("sync");
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if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
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out_be32(psurge_start, start);
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mb();
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psurge_set_ipi(nr);
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udelay(10);
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psurge_clr_ipi(nr);
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if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
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}
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/*
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* With the dual-cpu powersurge board, the decrementers and timebases
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* of both cpus are frozen after the secondary cpu is started up,
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* until we give the secondary cpu another interrupt. This routine
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* uses this to get the timebases synchronized.
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* -- paulus.
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*/
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static void __init psurge_dual_sync_tb(int cpu_nr)
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{
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int t;
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set_dec(tb_ticks_per_jiffy);
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set_tb(0, 0);
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last_jiffy_stamp(cpu_nr) = 0;
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if (cpu_nr > 0) {
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mb();
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sec_tb_reset = 1;
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return;
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}
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/* wait for the secondary to have reset its TB before proceeding */
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for (t = 10000000; t > 0 && !sec_tb_reset; --t)
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;
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/* now interrupt the secondary, starting both TBs */
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psurge_set_ipi(1);
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smp_tb_synchronized = 1;
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}
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static struct irqaction psurge_irqaction = {
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.handler = psurge_primary_intr,
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.flags = SA_INTERRUPT,
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.mask = CPU_MASK_NONE,
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.name = "primary IPI",
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};
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static void __init smp_psurge_setup_cpu(int cpu_nr)
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{
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if (cpu_nr == 0) {
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/* If we failed to start the second CPU, we should still
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* send it an IPI to start the timebase & DEC or we might
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* have them stuck.
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*/
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if (num_online_cpus() < 2) {
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if (psurge_type == PSURGE_DUAL)
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psurge_set_ipi(1);
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return;
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}
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/* reset the entry point so if we get another intr we won't
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* try to startup again */
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out_be32(psurge_start, 0x100);
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if (setup_irq(30, &psurge_irqaction))
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printk(KERN_ERR "Couldn't get primary IPI interrupt");
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}
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if (psurge_type == PSURGE_DUAL)
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psurge_dual_sync_tb(cpu_nr);
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}
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void __init smp_psurge_take_timebase(void)
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{
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/* Dummy implementation */
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}
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void __init smp_psurge_give_timebase(void)
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{
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/* Dummy implementation */
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}
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static int __init smp_core99_probe(void)
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{
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#ifdef CONFIG_6xx
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extern int powersave_nap;
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#endif
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struct device_node *cpus, *firstcpu;
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int i, ncpus = 0, boot_cpu = -1;
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u32 *tbprop = NULL;
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if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
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cpus = firstcpu = find_type_devices("cpu");
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while(cpus != NULL) {
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u32 *regprop = (u32 *)get_property(cpus, "reg", NULL);
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char *stateprop = (char *)get_property(cpus, "state", NULL);
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if (regprop != NULL && stateprop != NULL &&
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!strncmp(stateprop, "running", 7))
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boot_cpu = *regprop;
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++ncpus;
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cpus = cpus->next;
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}
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if (boot_cpu == -1)
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printk(KERN_WARNING "Couldn't detect boot CPU !\n");
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if (boot_cpu != 0)
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printk(KERN_WARNING "Boot CPU is %d, unsupported setup !\n", boot_cpu);
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if (machine_is_compatible("MacRISC4")) {
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extern struct smp_ops_t core99_smp_ops;
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core99_smp_ops.take_timebase = smp_generic_take_timebase;
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core99_smp_ops.give_timebase = smp_generic_give_timebase;
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} else {
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if (firstcpu != NULL)
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tbprop = (u32 *)get_property(firstcpu, "timebase-enable", NULL);
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if (tbprop)
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core99_tb_gpio = *tbprop;
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else
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core99_tb_gpio = KL_GPIO_TB_ENABLE;
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}
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if (ncpus > 1) {
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mpic_request_ipis();
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for (i = 1; i < ncpus; ++i)
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smp_hw_index[i] = i;
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#ifdef CONFIG_6xx
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powersave_nap = 0;
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#endif
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core99_init_caches(0);
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}
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return ncpus;
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}
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static void __devinit smp_core99_kick_cpu(int nr)
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{
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unsigned long save_vector, new_vector;
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unsigned long flags;
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volatile unsigned long *vector
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= ((volatile unsigned long *)(KERNELBASE+0x100));
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if (nr < 0 || nr > 3)
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return;
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if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu", 0x346);
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local_irq_save(flags);
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local_irq_disable();
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/* Save reset vector */
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save_vector = *vector;
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/* Setup fake reset vector that does
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* b __secondary_start_pmac_0 + nr*8 - KERNELBASE
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*/
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new_vector = (unsigned long) __secondary_start_pmac_0 + nr * 8;
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*vector = 0x48000002 + new_vector - KERNELBASE;
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/* flush data cache and inval instruction cache */
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flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
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/* Put some life in our friend */
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pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
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/* FIXME: We wait a bit for the CPU to take the exception, I should
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* instead wait for the entry code to set something for me. Well,
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* ideally, all that crap will be done in prom.c and the CPU left
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* in a RAM-based wait loop like CHRP.
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*/
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mdelay(1);
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/* Restore our exception vector */
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*vector = save_vector;
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flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
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local_irq_restore(flags);
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if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
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}
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static void __devinit smp_core99_setup_cpu(int cpu_nr)
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{
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/* Setup L2/L3 */
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if (cpu_nr != 0)
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core99_init_caches(cpu_nr);
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/* Setup openpic */
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mpic_setup_this_cpu();
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if (cpu_nr == 0) {
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#ifdef CONFIG_POWER4
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extern void g5_phy_disable_cpu1(void);
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/* If we didn't start the second CPU, we must take
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* it off the bus
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*/
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if (machine_is_compatible("MacRISC4") &&
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num_online_cpus() < 2)
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g5_phy_disable_cpu1();
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#endif /* CONFIG_POWER4 */
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if (ppc_md.progress) ppc_md.progress("core99_setup_cpu 0 done", 0x349);
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}
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}
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/* not __init, called in sleep/wakeup code */
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void smp_core99_take_timebase(void)
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{
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unsigned long flags;
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/* tell the primary we're here */
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sec_tb_reset = 1;
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mb();
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/* wait for the primary to set pri_tb_hi/lo */
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while (sec_tb_reset < 2)
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mb();
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/* set our stuff the same as the primary */
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local_irq_save(flags);
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set_dec(1);
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set_tb(pri_tb_hi, pri_tb_lo);
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last_jiffy_stamp(smp_processor_id()) = pri_tb_stamp;
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mb();
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/* tell the primary we're done */
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sec_tb_reset = 0;
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mb();
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local_irq_restore(flags);
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}
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/* not __init, called in sleep/wakeup code */
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void smp_core99_give_timebase(void)
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{
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unsigned long flags;
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unsigned int t;
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/* wait for the secondary to be in take_timebase */
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for (t = 100000; t > 0 && !sec_tb_reset; --t)
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udelay(10);
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if (!sec_tb_reset) {
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printk(KERN_WARNING "Timeout waiting sync on second CPU\n");
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return;
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}
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/* freeze the timebase and read it */
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/* disable interrupts so the timebase is disabled for the
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shortest possible time */
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local_irq_save(flags);
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pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
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pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
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mb();
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pri_tb_hi = get_tbu();
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pri_tb_lo = get_tbl();
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pri_tb_stamp = last_jiffy_stamp(smp_processor_id());
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mb();
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/* tell the secondary we're ready */
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sec_tb_reset = 2;
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mb();
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/* wait for the secondary to have taken it */
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for (t = 100000; t > 0 && sec_tb_reset; --t)
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udelay(10);
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if (sec_tb_reset)
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printk(KERN_WARNING "Timeout waiting sync(2) on second CPU\n");
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else
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smp_tb_synchronized = 1;
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/* Now, restart the timebase by leaving the GPIO to an open collector */
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pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
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pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
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local_irq_restore(flags);
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}
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void smp_core99_message_pass(int target, int msg, unsigned long data, int wait)
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{
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cpumask_t mask = CPU_MASK_ALL;
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/* make sure we're sending something that translates to an IPI */
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if (msg > 0x3) {
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printk("SMP %d: smp_message_pass: unknown msg %d\n",
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smp_processor_id(), msg);
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return;
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}
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switch (target) {
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case MSG_ALL:
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mpic_send_ipi(msg, cpus_addr(mask)[0]);
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break;
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case MSG_ALL_BUT_SELF:
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cpu_clear(smp_processor_id(), mask);
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mpic_send_ipi(msg, cpus_addr(mask)[0]);
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break;
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default:
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mpic_send_ipi(msg, 1 << target);
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break;
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}
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}
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/* PowerSurge-style Macs */
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struct smp_ops_t psurge_smp_ops = {
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.message_pass = smp_psurge_message_pass,
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.probe = smp_psurge_probe,
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.kick_cpu = smp_psurge_kick_cpu,
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.setup_cpu = smp_psurge_setup_cpu,
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.give_timebase = smp_psurge_give_timebase,
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.take_timebase = smp_psurge_take_timebase,
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};
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/* Core99 Macs (dual G4s) */
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struct smp_ops_t core99_smp_ops = {
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.message_pass = smp_core99_message_pass,
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.probe = smp_core99_probe,
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.kick_cpu = smp_core99_kick_cpu,
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.setup_cpu = smp_core99_setup_cpu,
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.give_timebase = smp_core99_give_timebase,
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.take_timebase = smp_core99_take_timebase,
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};
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#ifdef CONFIG_HOTPLUG_CPU
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int __cpu_disable(void)
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{
|
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cpu_clear(smp_processor_id(), cpu_online_map);
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|
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/* XXX reset cpu affinity here */
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|
mpic_cpu_set_priority(0xf);
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|
asm volatile("mtdec %0" : : "r" (0x7fffffff));
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mb();
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udelay(20);
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|
asm volatile("mtdec %0" : : "r" (0x7fffffff));
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return 0;
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}
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|
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extern void low_cpu_die(void) __attribute__((noreturn)); /* in pmac_sleep.S */
|
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static int cpu_dead[NR_CPUS];
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|
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void cpu_die(void)
|
|
{
|
|
local_irq_disable();
|
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cpu_dead[smp_processor_id()] = 1;
|
|
mb();
|
|
low_cpu_die();
|
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}
|
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|
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void __cpu_die(unsigned int cpu)
|
|
{
|
|
int timeout;
|
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|
|
timeout = 1000;
|
|
while (!cpu_dead[cpu]) {
|
|
if (--timeout == 0) {
|
|
printk("CPU %u refused to die!\n", cpu);
|
|
break;
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}
|
|
msleep(1);
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|
}
|
|
cpu_callin_map[cpu] = 0;
|
|
cpu_dead[cpu] = 0;
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}
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|
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#endif
|