forked from Minki/linux
664f8e26b0
vmx_complete_interrupts() assumes that the exception is always injected, so it can be dropped by kvm_clear_exception_queue(). However, an exception cannot be injected immediately if it is: 1) originally destined to a nested guest; 2) trapped to cause a vmexit; 3) happening right after VMLAUNCH/VMRESUME, i.e. when nested_run_pending is true. This patch applies to exceptions the same algorithm that is used for NMIs, replacing exception.reinject with "exception.injected" (equivalent to nmi_injected). exception.pending now represents an exception that is queued and whose side effects (e.g., update RFLAGS.RF or DR7) have not been applied yet. If exception.pending is true, the exception might result in a nested vmexit instead, too (in which case the side effects must not be applied). exception.injected instead represents an exception that is going to be injected into the guest at the next vmentry. Reported-by: Radim Krčmář <rkrcmar@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Signed-off-by: Wanpeng Li <wanpeng.li@hotmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
300 lines
7.2 KiB
C
300 lines
7.2 KiB
C
#ifndef ARCH_X86_KVM_X86_H
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#define ARCH_X86_KVM_X86_H
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#include <asm/processor.h>
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#include <asm/mwait.h>
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#include <linux/kvm_host.h>
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#include <asm/pvclock.h>
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#include "kvm_cache_regs.h"
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#define MSR_IA32_CR_PAT_DEFAULT 0x0007040600070406ULL
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static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.exception.injected = false;
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}
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static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector,
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bool soft)
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{
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vcpu->arch.interrupt.pending = true;
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vcpu->arch.interrupt.soft = soft;
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vcpu->arch.interrupt.nr = vector;
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}
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static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.interrupt.pending = false;
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}
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static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.exception.injected || vcpu->arch.interrupt.pending ||
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vcpu->arch.nmi_injected;
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}
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static inline bool kvm_exception_is_soft(unsigned int nr)
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{
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return (nr == BP_VECTOR) || (nr == OF_VECTOR);
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}
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static inline bool is_protmode(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr0_bits(vcpu, X86_CR0_PE);
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}
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static inline int is_long_mode(struct kvm_vcpu *vcpu)
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{
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#ifdef CONFIG_X86_64
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return vcpu->arch.efer & EFER_LMA;
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#else
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return 0;
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#endif
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}
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static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu)
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{
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int cs_db, cs_l;
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if (!is_long_mode(vcpu))
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return false;
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kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
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return cs_l;
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}
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static inline bool is_la57_mode(struct kvm_vcpu *vcpu)
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{
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#ifdef CONFIG_X86_64
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return (vcpu->arch.efer & EFER_LMA) &&
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kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
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#else
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return 0;
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#endif
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}
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static inline bool mmu_is_nested(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;
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}
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static inline int is_pae(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr4_bits(vcpu, X86_CR4_PAE);
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}
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static inline int is_pse(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr4_bits(vcpu, X86_CR4_PSE);
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}
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static inline int is_paging(struct kvm_vcpu *vcpu)
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{
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return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG));
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}
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static inline u32 bit(int bitno)
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{
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return 1 << (bitno & 31);
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}
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static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48;
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}
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static inline u8 ctxt_virt_addr_bits(struct x86_emulate_ctxt *ctxt)
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{
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return (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_LA57) ? 57 : 48;
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}
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static inline u64 get_canonical(u64 la, u8 vaddr_bits)
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{
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return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits);
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}
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static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu)
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{
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#ifdef CONFIG_X86_64
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return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la;
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#else
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return false;
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#endif
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}
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static inline bool emul_is_noncanonical_address(u64 la,
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struct x86_emulate_ctxt *ctxt)
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{
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#ifdef CONFIG_X86_64
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return get_canonical(la, ctxt_virt_addr_bits(ctxt)) != la;
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#else
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return false;
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#endif
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}
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static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
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gva_t gva, gfn_t gfn, unsigned access)
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{
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/*
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* If this is a shadow nested page table, the "GVA" is
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* actually a nGPA.
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*/
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vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK;
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vcpu->arch.access = access;
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vcpu->arch.mmio_gfn = gfn;
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vcpu->arch.mmio_gen = kvm_memslots(vcpu->kvm)->generation;
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}
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static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation;
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}
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/*
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* Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we
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* clear all mmio cache info.
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*/
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#define MMIO_GVA_ANY (~(gva_t)0)
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static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
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{
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if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
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return;
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vcpu->arch.mmio_gva = 0;
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}
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static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
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{
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if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva &&
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vcpu->arch.mmio_gva == (gva & PAGE_MASK))
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return true;
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return false;
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}
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static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
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{
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if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn &&
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vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
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return true;
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return false;
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}
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static inline unsigned long kvm_register_readl(struct kvm_vcpu *vcpu,
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enum kvm_reg reg)
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{
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unsigned long val = kvm_register_read(vcpu, reg);
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return is_64_bit_mode(vcpu) ? val : (u32)val;
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}
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static inline void kvm_register_writel(struct kvm_vcpu *vcpu,
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enum kvm_reg reg,
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unsigned long val)
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{
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if (!is_64_bit_mode(vcpu))
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val = (u32)val;
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return kvm_register_write(vcpu, reg, val);
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}
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static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
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{
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return !(kvm->arch.disabled_quirks & quirk);
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}
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void kvm_before_handle_nmi(struct kvm_vcpu *vcpu);
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void kvm_after_handle_nmi(struct kvm_vcpu *vcpu);
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void kvm_set_pending_timer(struct kvm_vcpu *vcpu);
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int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
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void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr);
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u64 get_kvmclock_ns(struct kvm *kvm);
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int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
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gva_t addr, void *val, unsigned int bytes,
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struct x86_exception *exception);
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int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
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gva_t addr, void *val, unsigned int bytes,
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struct x86_exception *exception);
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void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu);
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u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
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bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data);
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int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
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int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
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bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn,
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int page_num);
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bool kvm_vector_hashing_enabled(void);
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#define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
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| XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
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| XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
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| XFEATURE_MASK_PKRU)
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extern u64 host_xcr0;
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extern u64 kvm_supported_xcr0(void);
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extern unsigned int min_timer_period_us;
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extern unsigned int lapic_timer_advance_ns;
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extern struct static_key kvm_no_apic_vcpu;
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static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
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{
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return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
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vcpu->arch.virtual_tsc_shift);
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}
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/* Same "calling convention" as do_div:
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* - divide (n << 32) by base
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* - put result in n
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* - return remainder
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*/
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#define do_shl32_div32(n, base) \
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({ \
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u32 __quot, __rem; \
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asm("divl %2" : "=a" (__quot), "=d" (__rem) \
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: "rm" (base), "0" (0), "1" ((u32) n)); \
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n = __quot; \
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__rem; \
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})
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static inline bool kvm_mwait_in_guest(void)
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{
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unsigned int eax, ebx, ecx, edx;
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if (!cpu_has(&boot_cpu_data, X86_FEATURE_MWAIT))
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return false;
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_AMD:
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/* All AMD CPUs have a working MWAIT implementation */
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return true;
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case X86_VENDOR_INTEL:
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/* Handle Intel below */
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break;
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default:
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return false;
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}
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/*
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* Intel CPUs without CPUID5_ECX_INTERRUPT_BREAK are problematic as
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* they would allow guest to stop the CPU completely by disabling
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* interrupts then invoking MWAIT.
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*/
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if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
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return false;
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cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
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if (!(ecx & CPUID5_ECX_INTERRUPT_BREAK))
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return false;
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return true;
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}
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#endif
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