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c07cbc1f04
linux/drivers/gpu/drm/amd/display
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Yongqiang Sun c07cbc1f04 drm/amd/display: update dpp dto phase and modulo. 
[Why & How]
Program modulo with ref dpp clk Mhz/10.
Program phase with pipe dpp clk Mhz /10.
DMUB FW could use these value to determine optimization clk
for PSR power saving.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10 14:25:38 -05:00
..
amdgpu_dm drm/amd/display: Engage PSR synchronously 2020-11-10 14:24:55 -05:00
dc drm/amd/display: update dpp dto phase and modulo. 2020-11-10 14:25:38 -05:00
dmub drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3) 2020-11-04 17:11:37 -05:00
include Linux 5.10-rc3 2020-11-10 14:36:36 +01:00
modules drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3) 2020-11-04 17:11:37 -05:00
Kconfig drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3) 2020-11-04 17:11:37 -05:00
Makefile drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards 2019-11-13 15:29:42 -05:00
TODO