forked from Minki/linux
7ed220d738
Fixes 3D apps timing out in the WAIT_VBLANK ioctl. AVIVO bits compile-tested only. Signed-off-by: Michel Dänzer <daenzer@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
412 lines
11 KiB
C
412 lines
11 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include "drmP.h"
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#include "radeon_reg.h"
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#include "radeon.h"
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/* rs600 depends on : */
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void r100_hdp_reset(struct radeon_device *rdev);
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int r100_gui_wait_for_idle(struct radeon_device *rdev);
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int r300_mc_wait_for_idle(struct radeon_device *rdev);
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void r420_pipes_init(struct radeon_device *rdev);
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/* This files gather functions specifics to :
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* rs600
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*
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* Some of these functions might be used by newer ASICs.
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*/
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void rs600_gpu_init(struct radeon_device *rdev);
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int rs600_mc_wait_for_idle(struct radeon_device *rdev);
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void rs600_disable_vga(struct radeon_device *rdev);
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/*
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* GART.
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*/
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void rs600_gart_tlb_flush(struct radeon_device *rdev)
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{
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uint32_t tmp;
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tmp = RREG32_MC(RS600_MC_PT0_CNTL);
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tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
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WREG32_MC(RS600_MC_PT0_CNTL, tmp);
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tmp = RREG32_MC(RS600_MC_PT0_CNTL);
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tmp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
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WREG32_MC(RS600_MC_PT0_CNTL, tmp);
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tmp = RREG32_MC(RS600_MC_PT0_CNTL);
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tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
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WREG32_MC(RS600_MC_PT0_CNTL, tmp);
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tmp = RREG32_MC(RS600_MC_PT0_CNTL);
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}
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int rs600_gart_enable(struct radeon_device *rdev)
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{
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uint32_t tmp;
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int i;
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int r;
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/* Initialize common gart structure */
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r = radeon_gart_init(rdev);
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if (r) {
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return r;
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}
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rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
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r = radeon_gart_table_vram_alloc(rdev);
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if (r) {
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return r;
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}
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/* FIXME: setup default page */
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WREG32_MC(RS600_MC_PT0_CNTL,
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(RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
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RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
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for (i = 0; i < 19; i++) {
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WREG32_MC(RS600_MC_PT0_CLIENT0_CNTL + i,
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(RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
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RS600_SYSTEM_ACCESS_MODE_IN_SYS |
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RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE |
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RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
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RS600_ENABLE_FRAGMENT_PROCESSING |
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RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
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}
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/* System context map to GART space */
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WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_location);
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tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
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WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, tmp);
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/* enable first context */
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WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_location);
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tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
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WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR, tmp);
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WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL,
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(RS600_ENABLE_PAGE_TABLE | RS600_PAGE_TABLE_TYPE_FLAT));
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/* disable all other contexts */
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for (i = 1; i < 8; i++) {
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WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
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}
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/* setup the page table */
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WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
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rdev->gart.table_addr);
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WREG32_MC(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
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/* enable page tables */
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tmp = RREG32_MC(RS600_MC_PT0_CNTL);
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WREG32_MC(RS600_MC_PT0_CNTL, (tmp | RS600_ENABLE_PT));
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tmp = RREG32_MC(RS600_MC_CNTL1);
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WREG32_MC(RS600_MC_CNTL1, (tmp | RS600_ENABLE_PAGE_TABLES));
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rs600_gart_tlb_flush(rdev);
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rdev->gart.ready = true;
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return 0;
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}
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void rs600_gart_disable(struct radeon_device *rdev)
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{
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uint32_t tmp;
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/* FIXME: disable out of gart access */
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WREG32_MC(RS600_MC_PT0_CNTL, 0);
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tmp = RREG32_MC(RS600_MC_CNTL1);
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tmp &= ~RS600_ENABLE_PAGE_TABLES;
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WREG32_MC(RS600_MC_CNTL1, tmp);
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radeon_object_kunmap(rdev->gart.table.vram.robj);
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radeon_object_unpin(rdev->gart.table.vram.robj);
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}
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#define R600_PTE_VALID (1 << 0)
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#define R600_PTE_SYSTEM (1 << 1)
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#define R600_PTE_SNOOPED (1 << 2)
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#define R600_PTE_READABLE (1 << 5)
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#define R600_PTE_WRITEABLE (1 << 6)
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int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
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{
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void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
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if (i < 0 || i > rdev->gart.num_gpu_pages) {
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return -EINVAL;
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}
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addr = addr & 0xFFFFFFFFFFFFF000ULL;
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addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
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addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
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writeq(addr, ((void __iomem *)ptr) + (i * 8));
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return 0;
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}
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/*
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* MC.
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*/
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void rs600_mc_disable_clients(struct radeon_device *rdev)
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{
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unsigned tmp;
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if (r100_gui_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait GUI idle while "
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"programming pipes. Bad things might happen.\n");
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}
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tmp = RREG32(AVIVO_D1VGA_CONTROL);
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WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
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tmp = RREG32(AVIVO_D2VGA_CONTROL);
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WREG32(AVIVO_D2VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
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tmp = RREG32(AVIVO_D1CRTC_CONTROL);
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WREG32(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
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tmp = RREG32(AVIVO_D2CRTC_CONTROL);
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WREG32(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
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/* make sure all previous write got through */
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tmp = RREG32(AVIVO_D2CRTC_CONTROL);
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mdelay(1);
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}
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int rs600_mc_init(struct radeon_device *rdev)
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{
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uint32_t tmp;
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int r;
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if (r100_debugfs_rbbm_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for RBBM !\n");
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}
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rs600_gpu_init(rdev);
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rs600_gart_disable(rdev);
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/* Setup GPU memory space */
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rdev->mc.vram_location = 0xFFFFFFFFUL;
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rdev->mc.gtt_location = 0xFFFFFFFFUL;
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r = radeon_mc_setup(rdev);
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if (r) {
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return r;
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}
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/* Program GPU memory space */
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/* Enable bus master */
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tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
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WREG32(RADEON_BUS_CNTL, tmp);
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/* FIXME: What does AGP means for such chipset ? */
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WREG32_MC(RS600_MC_AGP_LOCATION, 0x0FFFFFFF);
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/* FIXME: are this AGP reg in indirect MC range ? */
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WREG32_MC(RS600_MC_AGP_BASE, 0);
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WREG32_MC(RS600_MC_AGP_BASE_2, 0);
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rs600_mc_disable_clients(rdev);
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if (rs600_mc_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait MC idle while "
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"programming pipes. Bad things might happen.\n");
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}
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tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
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tmp = REG_SET(RS600_MC_FB_TOP, tmp >> 16);
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tmp |= REG_SET(RS600_MC_FB_START, rdev->mc.vram_location >> 16);
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WREG32_MC(RS600_MC_FB_LOCATION, tmp);
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WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
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return 0;
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}
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void rs600_mc_fini(struct radeon_device *rdev)
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{
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rs600_gart_disable(rdev);
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radeon_gart_table_vram_free(rdev);
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radeon_gart_fini(rdev);
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}
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/*
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* Interrupts
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*/
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int rs600_irq_set(struct radeon_device *rdev)
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{
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uint32_t tmp = 0;
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uint32_t mode_int = 0;
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if (rdev->irq.sw_int) {
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tmp |= RADEON_SW_INT_ENABLE;
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}
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if (rdev->irq.crtc_vblank_int[0]) {
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tmp |= AVIVO_DISPLAY_INT_STATUS;
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mode_int |= AVIVO_D1MODE_INT_MASK;
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}
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if (rdev->irq.crtc_vblank_int[1]) {
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tmp |= AVIVO_DISPLAY_INT_STATUS;
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mode_int |= AVIVO_D2MODE_INT_MASK;
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}
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WREG32(RADEON_GEN_INT_CNTL, tmp);
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WREG32(AVIVO_DxMODE_INT_MASK, mode_int);
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return 0;
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}
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static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
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{
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uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
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uint32_t irq_mask = RADEON_SW_INT_TEST;
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if (irqs & AVIVO_DISPLAY_INT_STATUS) {
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*r500_disp_int = RREG32(AVIVO_DISP_INTERRUPT_STATUS);
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if (*r500_disp_int & AVIVO_D1_VBLANK_INTERRUPT) {
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WREG32(AVIVO_D1MODE_VBLANK_STATUS, AVIVO_VBLANK_ACK);
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}
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if (*r500_disp_int & AVIVO_D2_VBLANK_INTERRUPT) {
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WREG32(AVIVO_D2MODE_VBLANK_STATUS, AVIVO_VBLANK_ACK);
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}
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} else {
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*r500_disp_int = 0;
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}
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if (irqs) {
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WREG32(RADEON_GEN_INT_STATUS, irqs);
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}
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return irqs & irq_mask;
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}
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int rs600_irq_process(struct radeon_device *rdev)
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{
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uint32_t status;
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uint32_t r500_disp_int;
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status = rs600_irq_ack(rdev, &r500_disp_int);
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if (!status && !r500_disp_int) {
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return IRQ_NONE;
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}
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while (status || r500_disp_int) {
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/* SW interrupt */
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if (status & RADEON_SW_INT_TEST) {
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radeon_fence_process(rdev);
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}
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/* Vertical blank interrupts */
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if (r500_disp_int & AVIVO_D1_VBLANK_INTERRUPT) {
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drm_handle_vblank(rdev->ddev, 0);
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}
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if (r500_disp_int & AVIVO_D2_VBLANK_INTERRUPT) {
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drm_handle_vblank(rdev->ddev, 1);
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}
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status = rs600_irq_ack(rdev, &r500_disp_int);
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}
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return IRQ_HANDLED;
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}
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u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
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{
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if (crtc == 0)
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return RREG32(AVIVO_D1CRTC_FRAME_COUNT);
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else
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return RREG32(AVIVO_D2CRTC_FRAME_COUNT);
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}
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/*
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* Global GPU functions
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*/
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void rs600_disable_vga(struct radeon_device *rdev)
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{
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unsigned tmp;
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WREG32(0x330, 0);
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WREG32(0x338, 0);
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tmp = RREG32(0x300);
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tmp &= ~(3 << 16);
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WREG32(0x300, tmp);
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WREG32(0x308, (1 << 8));
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WREG32(0x310, rdev->mc.vram_location);
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WREG32(0x594, 0);
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}
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int rs600_mc_wait_for_idle(struct radeon_device *rdev)
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{
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unsigned i;
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uint32_t tmp;
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for (i = 0; i < rdev->usec_timeout; i++) {
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/* read MC_STATUS */
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tmp = RREG32_MC(RS600_MC_STATUS);
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if (tmp & RS600_MC_STATUS_IDLE) {
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return 0;
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}
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DRM_UDELAY(1);
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}
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return -1;
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}
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void rs600_errata(struct radeon_device *rdev)
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{
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rdev->pll_errata = 0;
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}
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void rs600_gpu_init(struct radeon_device *rdev)
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{
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/* FIXME: HDP same place on rs600 ? */
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r100_hdp_reset(rdev);
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rs600_disable_vga(rdev);
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/* FIXME: is this correct ? */
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r420_pipes_init(rdev);
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if (rs600_mc_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait MC idle while "
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"programming pipes. Bad things might happen.\n");
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}
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}
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/*
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* VRAM info.
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*/
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void rs600_vram_info(struct radeon_device *rdev)
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{
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/* FIXME: to do or is these values sane ? */
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rdev->mc.vram_is_ddr = true;
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rdev->mc.vram_width = 128;
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}
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void rs600_bandwidth_update(struct radeon_device *rdev)
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{
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/* FIXME: implement, should this be like rs690 ? */
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}
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/*
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* Indirect registers accessor
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*/
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uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
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{
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uint32_t r;
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WREG32(RS600_MC_INDEX,
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((reg & RS600_MC_ADDR_MASK) | RS600_MC_IND_CITF_ARB0));
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r = RREG32(RS600_MC_DATA);
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return r;
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}
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void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
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{
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WREG32(RS600_MC_INDEX,
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RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 |
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((reg) & RS600_MC_ADDR_MASK));
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WREG32(RS600_MC_DATA, v);
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}
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