25fdd5933e
SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a
top level wrapper consisting of Display Processing Unit (DPU) and
display peripheral modules such as Display Serial Interface (DSI)
and DisplayPort (DP).
MDSS functions essentially as a back-end composition engine. It blends
video and graphic images stored in the frame buffers and scans out the
composed image to a display sink (over DSI/DP).
The following diagram represents hardware blocks for a simple pipeline
(two planes are present on a given crtc which is connected to a DSI
connector):
MDSS
+---------------------------------+
| +-----------------------------+ |
| | DPU | |
| | +--------+ +--------+ | |
| | | SSPP | | SSPP | | |
| | +----+---+ +----+---+ | |
| | | | | |
| | +----v-----------v---+ | |
| | | Layer Mixer (LM) | | |
| | +--------------------+ | |
| | +--------------------+ | |
| | | PingPong (PP) | | |
| | +--------------------+ | |
| | +--------------------+ | |
| | | INTERFACE (VIDEO) | | |
| | +---+----------------+ | |
| +------|----------------------+ |
| | |
| +------|---------------------+ |
| | | DISPLAY PERIPHERALS | |
| | +---v-+ +-----+ | |
| | | DSI | | DP | | |
| | +-----+ +-----+ | |
| +----------------------------+ |
+---------------------------------+
The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs)
depends on SoC capabilities.
Overview of DPU sub-blocks:
---------------------------
* Source Surface Processor (SSPP):
Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are
capable of performing format conversion, scaling and quality improvement
for source surfaces.
* Layer Mixer (LM):
Blend source surfaces together (in requested zorder)
* PingPong (PP):
This block controls frame done interrupt output, EOL and EOF generation,
overflow/underflow control.
* Display interface (INTF):
Timing generator and interface connecting the display peripherals.
DRM components mapping to DPU architecture:
------------------------------------------
PLANEs maps to SSPPs
CRTC maps to LMs
Encoder maps to PPs, INTFs
Data flow setup:
---------------
MDSS hardware can support various data flows (e.g.):
- Dual pipe: Output from two LMs combined to single display.
- Split display: Output from two LMs connected to two separate
interfaces.
The hardware capabilities determine the number of concurrent data paths
possible. Any control path (i.e. pipeline w/i DPU) can be routed to any
of the hardware data paths. A given control path can be triggered,
flushed and controlled independently.
Changes in v3:
- Move msm_media_info.h from uapi to dpu/ subdir
- Remove preclose callback dpu (it's handled in core)
- Fix kbuild warnings with parent_ops
- Remove unused functions from dpu_core_irq
- Rename mdss_phys to mdss
- Rename mdp_phys address space to mdp
- Drop _phys from vbif and regdma binding names
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org>
Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
[robclark minor rebase]
Signed-off-by: Rob Clark <robdclark@gmail.com>
104 lines
2.5 KiB
C
104 lines
2.5 KiB
C
/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef DPU_DBG_H_
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#define DPU_DBG_H_
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#include <stdarg.h>
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#include <linux/debugfs.h>
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#include <linux/list.h>
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enum dpu_dbg_dump_flag {
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DPU_DBG_DUMP_IN_LOG = BIT(0),
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DPU_DBG_DUMP_IN_MEM = BIT(1),
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};
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#if defined(CONFIG_DEBUG_FS)
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/**
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* dpu_dbg_init_dbg_buses - initialize debug bus dumping support for the chipset
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* @hwversion: Chipset revision
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*/
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void dpu_dbg_init_dbg_buses(u32 hwversion);
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/**
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* dpu_dbg_init - initialize global dpu debug facilities: regdump
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* @dev: device handle
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* Returns: 0 or -ERROR
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*/
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int dpu_dbg_init(struct device *dev);
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/**
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* dpu_dbg_debugfs_register - register entries at the given debugfs dir
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* @debugfs_root: debugfs root in which to create dpu debug entries
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* Returns: 0 or -ERROR
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*/
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int dpu_dbg_debugfs_register(struct dentry *debugfs_root);
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/**
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* dpu_dbg_destroy - destroy the global dpu debug facilities
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* Returns: none
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*/
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void dpu_dbg_destroy(void);
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/**
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* dpu_dbg_dump - trigger dumping of all dpu_dbg facilities
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* @queue_work: whether to queue the dumping work to the work_struct
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* @name: string indicating origin of dump
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* @dump_dbgbus: dump the dpu debug bus
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* @dump_vbif_rt: dump the vbif rt bus
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* Returns: none
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*/
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void dpu_dbg_dump(bool queue_work, const char *name, bool dump_dbgbus_dpu,
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bool dump_dbgbus_vbif_rt);
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/**
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* dpu_dbg_set_dpu_top_offset - set the target specific offset from mdss base
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* address of the top registers. Used for accessing debug bus controls.
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* @blk_off: offset from mdss base of the top block
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*/
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void dpu_dbg_set_dpu_top_offset(u32 blk_off);
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#else
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static inline void dpu_dbg_init_dbg_buses(u32 hwversion)
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{
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}
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static inline int dpu_dbg_init(struct device *dev)
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{
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return 0;
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}
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static inline int dpu_dbg_debugfs_register(struct dentry *debugfs_root)
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{
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return 0;
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}
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static inline void dpu_dbg_destroy(void)
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{
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}
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static inline void dpu_dbg_dump(bool queue_work, const char *name,
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bool dump_dbgbus_dpu, bool dump_dbgbus_vbif_rt)
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{
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}
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static inline void dpu_dbg_set_dpu_top_offset(u32 blk_off)
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{
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}
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#endif /* defined(CONFIG_DEBUG_FS) */
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#endif /* DPU_DBG_H_ */
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