fb8d6c8db3
Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50 firmware. Cc: Andrey Pronin <apronin@chromium.org> Cc: Duncan Laurie <dlaurie@chromium.org> Cc: Jason Gunthorpe <jgg@ziepe.ca> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Guenter Roeck <groeck@chromium.org> Cc: Alexander Steffen <Alexander.Steffen@infineon.com> Cc: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Acked-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
20 lines
472 B
Plaintext
20 lines
472 B
Plaintext
* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus.
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H1 Secure Microcontroller running Cr50 firmware provides several
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functions, including TPM-like functionality. It communicates over
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SPI using the FIFO protocol described in the PTP Spec, section 6.
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Required properties:
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- compatible: Should be "google,cr50".
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- spi-max-frequency: Maximum SPI frequency.
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Example:
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&spi0 {
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tpm@0 {
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compatible = "google,cr50";
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reg = <0>;
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spi-max-frequency = <800000>;
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};
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};
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